1mo
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SoC Architecture and Design Engineer, Senior Member of Technical Staff (SMTS)
Richardson or Folsom
$177k-$334k/yr OnsiteFull Time
15+ YOEBachelors or Masters in electrical/computer engineering; 15+ years in related field; SystemVerilog/Verilog; RTL-to-GDS flow; Cadence/Synopsys/Siemens; Python/TCL/Perl.
SystemVerilog, Verilog, RTL, EDA tools (Cadence, Synopsys, Siemens), Python, TCL, Perl
1w
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Hardware Engineer - FPGA
Milpitas or San Francisco
$152k-$222k/yr OnsiteFull Time
7+ YOEExperienced FPGA/ASIC engineer with RTL (Verilog/SystemVerilog) skills, FPGA tool experience, 7+ years (BS) or 4+ years (MS), verification experience (UVM/VMM) preferred.
Verilog, SystemVerilog, UVM, VMM
3w
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Senior Technologist Datapath Design Engineer and Circuit Design Engineer, VLSI Design Engineering
Milpitas, California, United States
$194k-$322k/yr OnsiteFull Time
15+ YOEMaster's in Electrical Engineering (or equivalent) with 15+ years experience; transistor/gate-level datapath and page-buffer design; RTL/Verilog, synthesis, static timing, silicon debugging, and high-speed I/O knowledge.
Verilog
2mo
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Lead ASIC/FPGA Design Engineer
Livermore, California, United States
OnsiteFull Time
5+ YOELead RTL design of high-speed ASIC/FPGA modem; strong DSP, FEC integration, and power/performance optimizations; requires security clearance.
Verilog, SystemVerilog, LINT, CDC, RDC, Test benche s, Synthesis, Power/Area analysis, STA, Place and Route
1mo
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Senior Engineer Space Electronics
Pleasanton, California, United States
$142k-$186k/yr OnsiteFull Time
3+ YOEBachelor's in EE (or related) with 6+ yrs or Master's with 3+ yrs; 3+ yrs space/LEO electronics design; experience with power, analog, mixed‑signal, radiation testing/mitigation; LTSpice proficiency; high‑speed PCB design and lab test equipment experience; must be U.S. Person.
LTSpice, FPGA, MCU, RTL, AS9100, Oscilloscope, VNA, Spectrum Analyzer, Power Supply, Function Generator, DVM
6d
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Technologist, Systems Design Engineering
Milpitas, California, United States
$142k-$235k/yr OnsiteFull Time
Bachelor's in EE/CE/CS, strong experience in digital/system architecture, RTL development and debug (Verilog/SystemVerilog), firmware bring‑up, post‑silicon debug, Python/Bash/Tcl scripting, and cross‑layer root‑cause analysis.
Verilog, SystemVerilog, RTL, Python, Bash, Tcl, Firmware (FW), AI-assisted engineering tools
1mo
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Software Engineering Technical Leader , Frontend (Hybrid)
Milpitas or San Jose
$184k-$264k/yr HybridFull Time
8+ YOE8+ years frontend experience (React, TypeScript, modern JavaScript), experience with monorepos (Nx), module federation/microfrontend patterns, automated testing (Jest, RTL, Playwright), CI/CD, strong communication and collaboration skills.
React, TypeScript, JavaScript, Nx, pnpm, Yarn, Module Federation, Jest, React Testing Library, Playwright, Rspack, Webpack, React Router, TanStack Table, Framer Motion, React DnD, Amplitude, Sentry, GraphQL, REST
2w
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Principal / Lead DSP & Systems Architect — Ultra High-Speed SerDes
Milpitas, California, United States
OnsiteFull Time
10+ YOEGraduate degree in EE/Communications/Signal Processing (PhD preferred), 10+ years in high-speed SerDes or wireline/optical DSP/systems architecture, expertise in PAM/coherent signaling, FEC, ADC/DAC, MATLAB/Python modeling, and DSP-to-RTL methodology.
MATLAB, Python