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RTL Design Engineer
Cary, North Carolina, United States
OnsiteFull Time
Bachelor's in Electrical Engineering; RTL design, Verilog/SystemVerilog; mixed-signal concepts; scripting; GenAI experience preferred.
Verilog, SystemVerilog, Verilog simulators, linters, CDC, RDC, LEQ, UPF, Perl, Python, JSON, GenAI tools, Digital signal processing
2mo
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RISCV CPU System RTL Engineer
Santa Clara or San Diego or Austin or Raleigh
$142k-$213k/yr OnsiteFull Time
1+ YOEMaster's (1+ yr) or Bachelor's (2+ yrs) in EE/CE/CS; 1–3 years CPU RTL experience; deep microarchitecture knowledge; proficiency in Verilog/VHDL; experience with power management, debug/trace, and strong documentation and communication skills.
Verilog, VHDL, Perl, Python
4d
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Senior Memory Controller RTL Design Engineer
Redmond or Mountain View or Raleigh or Austin or Hillsboro
$120k-$235k/yr HybridFull Time
1+ YOEDegree in EE/CE/CS or equivalent with 1–5+ years experience depending on degree, strong Verilog/SystemVerilog RTL design skills, DDR4/DDR5 controller experience preferred, scripting (Perl/Tcl/Python), familiarity with front-end verification and low-power/timing checks, ability to pass Microsoft security and export control screenings.
Verilog, System Verilog, Perl, Tcl, Python
3w
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Principal Design Engineer
San Jose or Cary
$137k-$254k/yr OnsiteFull Time
1+ YOEBS/MS/PhD in Electrical Engineering with 7/5/1+ years respectively; experience with Cadence Innovus/Tempus/QRC/Voltus/Pegasus and Palladium/Protium; Linux and Shell/Perl/TCL scripting; RTL synthesis, floorplanning, timing closure, IR drop, and industry interfaces (PCIe, DDR, LPDDR, SRAM, UCIe).
Innovus, Tempus, QRC, Voltus, Pegasus, Palladium, Protium, Linux, Shell, Perl, TCL
2w
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Senior VHDL Firmware Engineer
Research Triangle Park, North Carolina, United States
RemoteFull Time
Bachelor's in Electrical Engineering required (Master's preferred). Experience with VHDL, C/C++, FPGA (AMD/Xilinx), RTL VHDL, embedded/real-time systems; Python, DSP or motor control helpful; up to 25% travel.
VHDL, C, C++, Python, FPGA, AMD, Xilinx, RTL, DSP
2w
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Senior Physical Design and Timing Engineer
Santa Clara or Austin or Hillsboro or Durham
$136k-$265k/yr HybridFull Time
3+ YOEBS in Electrical or Computer Engineering with 5+ years or MS with 3+ years; strong static timing analysis, synthesis, physical design, timing convergence, RTL/logic understanding; proficiency with Perl, Tcl, Make, Python.
Perl, Tcl, Make, Python
2w
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FPGA Systems Development Engineer
Copenhagen or Durham
OnsiteFull Time
Bachelor's in electrical/computer engineering, hands-on FPGA/SoC programming experience, strong communication and problem-solving, ability to work on multiple projects and deliver high-quality results.
FPGA, SoC, HDL, IP, RTL, Intel-Altera, AMD-Xilinx, C/C++, Python, TCL, ATE
3w
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Senior ASIC Design Engineer - Agentic AI
Santa Clara or Durham or Austin
$168k-$311k/yr OnsiteFull Time
8+ YOEMaster's/PhD or equivalent, 8+ years experience, expertise in micro-architecture and RTL (Verilog), ASIC design flow, Python proficiency, and experience with LLM fine-tuning, RAG pipelines and vector databases.
Verilog, Python, large language models, RAG pipelines, vector databases
1mo
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ASIC Physical Design Technical Lead
San Jose or Austin or Research Triangle Park
$184k-$264k/yr OnsiteFull Time
3+ YOEBachelor/Master/PhD in Electrical Engineering with 3+–8+ years physical design experience; RTL-to-GDSII tapeout experience at advanced nodes; experience with Innovus, Tempus/Primetime, Redhawk/Voltus, Calibre/Pegasus, UPF, and Python.
Innovus, Tempus, Primetime, Redhawk, Voltus, Calibre, Pegasus, Python, UPF
4w
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MTS Digital Engineering
Morrisville, North Carolina, United States
$58k-$108k/yr HybridFull Time
0+ YOEBS EE (2-3 years) or MS EE/CE (0-1 year). Strong digital RTL design experience with Verilog/SystemVerilog, STA/CDC/Lint/DFT/BIST tools, plus Python/Perl scripting and simulation/debug skills.
SystemVerilog, Verilog, Python, Perl, Static Timing Analysis (STA), LEC, CDC, RDC, Lint, DFT, BIST
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