68 rtl engineer jobs at 13 companies in Solana Beach, CA
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Processor ASIC RTL Design Engineer
San Diego, California, United States
$127k-$191k/yr OnsiteFull Time
2+ YOE2+ years RTL and microprocessor design experience; strong RTL design in System Verilog/Verilog, familiarity with linting, CDC, LEC, CLP, synthesis, static timing analysis, PLDRC, and low-power techniques; BS/MS/PhD in EE/CS/CE or related.
System Verilog, Verilog, RTL, GDS2, linting, CDC, LEC, CLP, synthesis, static timing analysis, PLDRC
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Staff/Sr. Staff GPU Engineer – Shader System RTL Design/Microarchitecture
San Diego, California, United States
$150k-$244k/yr OnsiteFull Time
8+ YOEBS/MS/PhD or equivalent,8+ years (Staff) /10+ years (Sr Staff) in RTL/microarchitecture for GPU or high-performance SoC; strong SystemVerilog/Verilog/VHDL,C/C++,Python skills; RTL debug, PPA optimization, and cross-team collaboration.
SystemVerilog, Verilog, VHDL, C, C++, Python, Perl, Tcl, Shell, Vulkan, Direct3D, OpenGL, OpenGL ES, Metal, OpenCL
2mo
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ASIC Design Engineer I, Satellite Communications
San Diego, California, United States
$123k-$170k/yr OnsiteFull Time
2+ YOEBachelor's in Electrical Engineering; 2+ years in digital logic/DSP design; RTL implementation; DSP algorithms optimization.
MATLAB, RTL, UVM, SystemC, DPI-C, Verilog, VHDL
3mo
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Wireless Design Engineer
San Diego or Sunnyvale
OnsiteFull Time
10+ YOEBS with 10+ years in relevant industry; ASIC/RTL design; MAC/wireless knowledge; HDL/SystemVerilog; scripting and power management experience.
Verilog, SystemVerilog, Python, Shell
2d
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Principal COE Digital Design Engineer
San Diego, California, United States
$160k-$237k/yr OnsiteFull Time
8+ YOEBachelor's or master's degree in electrical or electronics engineering and 8–10+ years of RTL design experience, including PCIe/CXL subsystems, SystemVerilog/Verilog, ARM SoC integration, AMBA, EDA tools, scripting, and version control.
SystemVerilog, Verilog, ARM, AMBA, AXI-4, CHI, ACE, TCL, Perl, Python, GIT, SVN, Synopsys, Cadence, Mentor, Siemens
2mo
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Design Verification Engineer - Viasat Government
Marlborough or Carlsbad
$133k-$210k/yr OnsiteFull Time
5+ YOEBachelor's in Electrical or Computer Engineering; 5+ years hardware verification with SystemVerilog/UVM; RTL verification; strong SystemVerilog/UVM; experience with industry EDA tools; US citizenship and active Secret clearance; willingness to travel up to 10%
SystemVerilog, UVM, Siemens Questa, Cadence, Synopsys, Mentor, Python, TCL
12h
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Senior Applications Engineer - Emulation
San Diego or Costa Mesa or Austin or Wilsonville
$147k-$293k/yr HybridFull Time
4+ YOERequires 4+ years in electronics design, verification, simulation, emulation, or prototyping; BS/MS in EE, CE, CS, or related field; RTL, verification, scripting, communication, and travel skills.
Veloce, Palladium, Zebu, SystemVerilog, Verilog, VHDL, SystemC, C, C++, Perl, Python, Makefiles, XML, JSON
3d
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Design Verification Engineer
Broomfield or San Diego or Fort Collins or San Jose or Irvine
$144k-$230k/yr OnsiteFull Time
10+ YOE12+ years verification experience for complex digital and mixed-signal circuits; proficiency with SystemVerilog/UVM/SVA, scripting, simulation tools, and RTL/gate-level debug; BS/MS in EE/CE.
SystemVerilog, UVM, SVA, Synopsys, Cadence, Mentor, Perl, Python, Tcl, DesignSync, git, Palladium, Veloce, Zebu, Xilinx, ICL, PDL, Tessent
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Senior Principal Engineer Digital ASIC Design/Manager
San Diego, California, United States
$214k-$348k/yr OnsiteFull Time
15+ YOEBS or MS in Electrical Engineering; 15 years in Digital ASIC design; leadership; cross-functional collaboration; RTL/verification; experience with mixed-signal interfaces is a plus.
Verilog, SystemVerilog, LINT, LEC, RDC/CDC, SDF, Genus, Conformal, Innovus, Spyglass Lint, TetraMax, Xcelium, Cadence, Synopsys PrimeTime, VCS, UGV, UVM
6d
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Senior TPU Design Engineer, Silicon
Mountain View or San Diego
$163k-$236k/yr OnsiteFull Time
8+ YOE4+ MgmtBachelor's in EE/CE/CS or equivalent,8+ years RTL design with Verilog/System Verilog,4+ years leading IP/SoC teams,ARM/ASIC experience,EM/FPGA bring-up and strong communication.
Verilog, System Verilog, ARM, FPGA
1mo
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Sr. Staff/Staff Engineer, Digital Design
San Diego or San Jose
OnsiteFull Time
Deep RTL/SystemVerilog expertise, SoC architecture knowledge, familiarity with AXI/AHB/APB/OBI, multi-clock/multi-power-domain and timing closure experience, skills with SystemVerilog, Python, Tcl, UPF, and security technologies (Arm TrustZone, Secure Boot, PSA Level 2+); MS/PhD preferred.
SystemVerilog, Python, Tcl, UPF, AXI, AHB, APB, OBI, Arm TrustZone
1w
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Principal Modem PHY IP Design Verification Engineer - Terawave
Texas or California or San Diego
$269k-$377k/yr OnsiteFull Time
Blue Origin: Develops reusable rockets and systems for human spaceflight.
10+ YOEBachelor's in EE/CE/CS,10+ years verification experience, SystemVerilog and UVM expertise, modem PHY/DSP familiarity, scripting with Python/Perl/shell, strong RTL/testbench debugging, ability to work with cross-functional teams.
SystemVerilog, UVM, Python, Perl, shell, MATLAB, C/C++
1w
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Field Application Engineer – PowerPro
Austin or Costa Mesa or San Diego or Santa Clara
$147k-$293k/yr HybridFull Time
3+ YOE3+ years RTL design experience with Verilog/SystemVerilog/VHDL, RTL power analysis knowledge, scripting with Tcl/Python, BS/MS in EE/CS or related, strong communication and customer-facing skills.
PowerPro, Verilog, SystemVerilog, VHDL, Tcl, Python, PrimePower, PowerArtist, UPF, CPF
1mo
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Sr. Principal Digital Design Verification Lead
San Diego, California, United States
$142k-$213k/yr HybridFull Time
6+ YOEExperience in FPGA verification using SystemVerilog/UVM, Questa/ModelSim, scripting (Python/Tcl/Bash), Git, RTL (Verilog/VHDL); ability to obtain US Secret clearance and Program Access (PAR).
SystemVerilog, UVM, Questa, ModelSim, Verilog, VHDL, SVA, Python, Tcl, Bash, Git
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Sr. Principal Digital Design Verification Lead
San Diego, California, United States
$142k-$213k/yr HybridFull Time
5+ YOE5+ years FPGA verification experience, strong SystemVerilog/UVM skills, Questa/ModelSim experience, RTL knowledge (Verilog/VHDL), scripting (Python/Tcl/Bash), Git, and ability to obtain US Secret clearance and Program Access.
SystemVerilog, UVM, Questa, ModelSim, Verilog, VHDL, SVA, Python, Tcl, Bash, Git
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