12 rtl engineer jobs at 8 companies in Stockton, CA
2mo
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SoC Architecture and Design Engineer, Senior Member of Technical Staff (SMTS)
Richardson or Folsom
$177k-$334k/yr OnsiteFull Time
15+ YOEBachelors or Masters in electrical/computer engineering; 15+ years in related field; SystemVerilog/Verilog; RTL-to-GDS flow; Cadence/Synopsys/Siemens; Python/TCL/Perl.
SystemVerilog, Verilog, RTL, EDA tools (Cadence, Synopsys, Siemens), Python, TCL, Perl
3w
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Hardware Engineer - FPGA
Milpitas or San Francisco
$152k-$222k/yr OnsiteFull Time
7+ YOEExperienced FPGA/ASIC engineer with RTL (Verilog/SystemVerilog) skills, FPGA tool experience, 7+ years (BS) or 4+ years (MS), verification experience (UVM/VMM) preferred.
Verilog, SystemVerilog, UVM, VMM
1mo
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IP Logic Design Engineer
Rancho Cordova, California, United States
$105k-$165k/yr OnsiteFull Time
7+ YOEMS in ECE with 7+ years or BS with 9+ years; expertise in Verilog/SystemVerilog and ASIC flow (RTL, synthesis, STA, ECO); experience with lint, CDC/RDC analysis, verification tools, scripting, and pre/post-silicon debug; 3D NAND experience preferred.
SystemVerilog, Verilog, RTL, synthesis, Static Timing Analysis (STA), ECO, lint tools, CDC/RDC analysis, SystemVerilog Assertions (SVAs), Gate-level simulation (GLS), Design for Testability (DFT)
2mo
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Staff Engineer - ASIC Verification
San Jose or Folsom
$145k-$286k/yr OnsiteFull Time
6+ YOEBS in electrical engineering or computer science; 6-8 years verification; RTL debugging, scoreboarding, and code coverage; test plans and coverage definitions.
SystemVerilog, UVM, C, DDR, PCIe/NVMe, NAND
5d
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Hardware Engineer
Colorado Springs or Irvine or Longmont or Fremont or Rochester or San Jose
$91k-$113k/yr OnsiteFull Time
Early-career candidates pursuing or recently completing an engineering degree; familiarity with hardware, firmware, ASIC/SoC, or systems; programming and design experience through coursework or projects; strong analytical and communication skills.
Verilog/SystemVerilog, RTL, FPGA, C, C++, Assembly, Python, Java, Go, SQL, JavaScript, Git, Linux, IDE, CAD, Microsoft Office, RTOS
1mo
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Senior Technologist Datapath Design Engineer and Circuit Design Engineer, VLSI Design Engineering
Milpitas, California, United States
$194k-$322k/yr OnsiteFull Time
15+ YOEMaster's in Electrical Engineering (or equivalent) with 15+ years experience; transistor/gate-level datapath and page-buffer design; RTL/Verilog, synthesis, static timing, silicon debugging, and high-speed I/O knowledge.
Verilog
1mo
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Senior Engineer Space Electronics
Pleasanton, California, United States
$142k-$186k/yr OnsiteFull Time
3+ YOEBachelor's in EE (or related) with 6+ yrs or Master's with 3+ yrs; 3+ yrs space/LEO electronics design; experience with power, analog, mixed‑signal, radiation testing/mitigation; LTSpice proficiency; high‑speed PCB design and lab test equipment experience; must be U.S. Person.
LTSpice, FPGA, MCU, RTL, AS9100, Oscilloscope, VNA, Spectrum Analyzer, Power Supply, Function Generator, DVM
5d
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Summer 2027 Intern - Hardware Engineering
Colorado Springs or Irvine or Longmont or Fremont or Rochester or San Jose
$34-$47/hr HybridInternship
0+ YOEEarly-career candidates pursuing or holding technical degrees in engineering or related fields; experience via coursework, internships, projects; familiarity with programming, embedded systems, digital logic, or hardware design; strong analytical and communication skills.
RTL, Verilog/SystemVerilog, FPGA, C, C++, Assembly, Python, Java, Go, SQL, JavaScript, CAD, Git, Linux, Microsoft Office, RTOS
2d
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Senior Principal AI System Architect
Milpitas, California, United States
$194k-$322k/yr HybridFull Time
10+ YOEMaster's or Ph.D. in EE/CE/CS,10+ years in system/SoC architecture and memory system development, strong C/C++ and Python skills, RTL and system-level modeling experience, knowledge of memory technologies and interconnects.
C/C++, Python, RTL, SoC, GPU, DRAM, DDR, LPDDR, GDDR, NAND, PCIe, CXL, NoCs, ethernet, RDMA
2d
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AI/ML ASIC Architect
Milpitas, California, United States
$194k-$322k/yr HybridFull Time
15+ YOEBachelors (or Masters/PhD) in Computer/Electrical Engineering with 15+ years architecture experience; deep expertise in PCIe/UCIe/CXL, DMA, SoC, HBM, ML/AI accelerator architecture; strong microarchitecture and system-level design skills.
UCIe, PCIe, CXL, DMA, NoC, FPGA, RTL, DV, Simulation, Emulation, Firmware, HBM, CUDA, NVLink, InfiniBand, RDMA, NVMe, NAND, AXI, MX format
1mo
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Principal / Lead DSP & Systems Architect — Ultra High-Speed SerDes
Milpitas, California, United States
OnsiteFull Time
10+ YOEGraduate degree in EE/Communications/Signal Processing (PhD preferred), 10+ years in high-speed SerDes or wireline/optical DSP/systems architecture, expertise in PAM/coherent signaling, FEC, ADC/DAC, MATLAB/Python modeling, and DSP-to-RTL methodology.
MATLAB, Python
1mo
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GPU Performance Architect
Folsom or Santa Clara
$127k-$217k/yr HybridFull Time
Develop performance models and prototypes for GPU/SoC systems; analyze ML/HPC workloads; write and optimize GPU kernels; strong programming in C/C++/Python; knowledge of CUDA/OpenCL and ML frameworks.
TensorFlow, PyTorch, CUDA, OpenCL, C, C++, Python, Hip, Triton, MLIR, LLVM, RTL, System C