EndoSec: Security software and cryptographic hardware for government and defense.
Design, develop, test, and maintain FPGA IP cores and FPGA-based systems for hardware security; RTL/C/C++, Python, VHDL/Verilog; simulation, verification, system integration; verification tools and toolchains.
AmazonNASDAQ: AMZN: Global online retail and cloud computing technology provider.
5+ YOEBachelor's degree in Electrical Engineering; 5+ years design/architecture experience; RTL coding with VHDL/SystemVerilog/Verilog; knowledge of IT hardware and networks; 5+ years FPGA RTL development.
Sparton: Produces sonobuoys and undersea sensors for maritime defense.
5+ YOEU.S. citizen able to obtain security clearance. 5+ years RTL FPGA design (VHDL/Verilog/SystemVerilog), FPGA implementation of image/signal processing, experience with Xilinx devices, high-speed interfaces, MATLAB/Python/C++, Vitis HLS/AI, and Linux driver development.
Trident Systems: Develops high-performance electronics for space and defense.
4+ YOEBachelor's in EE/CE (or MS) and 6+ years (4+ with MS) experience in FPGA RTL design, timing closure, simulation/verification, Vivado/VHDL/SystemVerilog experience, lab bring‑up, and high‑speed interface integration.
Northrop GrummanNYSE: NOC: Develops and manufactures advanced aerospace, defense, and space systems.
5+ YOEExperience with VHDL and FPGA design flow, ability to obtain Top Secret/SCI clearance, degree in engineering with relevant years of experience, FPGA verification and architecture experience, and recent hands-on VHDL work.
Booz Allen HamiltonNYSE: BAH: Provides technology and management consulting services to diverse organizations.
3+ YOE3+ years developing FPGA/SDR solutions; proficiency with Verilog/VHDL/SystemVerilog/HLS, Vitis/Vivado/Xilinx toolchains, Python/C++, MATLAB, Linux, Agile tools (Jira, Confluence); ability to obtain TS/SCI clearance; bachelor’s in EE or CE required.
Northrop GrummanNYSE: NOC: Develops and manufactures advanced aerospace, defense, and space systems.
5+ YOEBS with 5+ yrs or MS with 3+ yrs (Level 3) or PhD with 1+ yrs; SCI clearance; VHDL experience; FPGA design flow expertise; aerospace domain knowledge; leadership experience.
VHDL, RTL, Synthesis, Place and Route, Timing Analysis, Power Analysis, Vivado, QuestaSim, MATLAB, Simulink
Associated Universities, Inc.: Manages and operates world-class scientific research facilities.
8+ YOEBachelor's in electrical engineering or related; 8+ years developing complex FPGA-based DSP systems; experience leading FPGA architecture, RTL development, timing analysis, and system integration; strong communication and leadership.