3mo
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RTL Design Engineer
Cary, North Carolina, United States
OnsiteFull Time
Bachelor's in Electrical Engineering; RTL design, Verilog/SystemVerilog; mixed-signal concepts; scripting; GenAI experience preferred.
Verilog, SystemVerilog, Verilog simulators, linters, CDC, RDC, LEQ, UPF, Perl, Python, JSON, GenAI tools, Digital signal processing
2mo
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RISCV CPU System RTL Engineer
Santa Clara or San Diego or Austin or Raleigh
$142k-$213k/yr OnsiteFull Time
1+ YOEMaster's (1+ yr) or Bachelor's (2+ yrs) in EE/CE/CS; 1–3 years CPU RTL experience; deep microarchitecture knowledge; proficiency in Verilog/VHDL; experience with power management, debug/trace, and strong documentation and communication skills.
Verilog, VHDL, Perl, Python
6d
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Senior Memory Controller RTL Design Engineer
Redmond or Mountain View or Raleigh or Austin or Hillsboro
$120k-$235k/yr HybridFull Time
1+ YOEDegree in EE/CE/CS or equivalent with 1–5+ years experience depending on degree, strong Verilog/SystemVerilog RTL design skills, DDR4/DDR5 controller experience preferred, scripting (Perl/Tcl/Python), familiarity with front-end verification and low-power/timing checks, ability to pass Microsoft security and export control screenings.
Verilog, System Verilog, Perl, Tcl, Python
3w
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Principal Design Engineer
San Jose or Cary
$137k-$254k/yr OnsiteFull Time
1+ YOEBS/MS/PhD in Electrical Engineering with 7/5/1+ years respectively; experience with Cadence Innovus/Tempus/QRC/Voltus/Pegasus and Palladium/Protium; Linux and Shell/Perl/TCL scripting; RTL synthesis, floorplanning, timing closure, IR drop, and industry interfaces (PCIe, DDR, LPDDR, SRAM, UCIe).
Innovus, Tempus, QRC, Voltus, Pegasus, Palladium, Protium, Linux, Shell, Perl, TCL
2d
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Senior Silicon Engineer
Redmond or Mountain View or Santa Clara or Austin or Raleigh or Hillsboro or Boise
$120k-$235k/yr HybridFull Time
5+ YOEExperience verifying silicon using UVM/C, strong RTL and SoC verification background, proficiency with Verilog/System Verilog, and relevant EE/CS/CE degree or equivalent experience.
UVM, C, Verilog, System Verilog, Microsoft Excel
1w
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Principal Firmware Engineer
Mountain View or Redmond or Hillsboro or Raleigh or Austin
$143k-$275k/yr HybridFull Time
SoC/firmware architecting, silicon bring-up, root-cause debug across RTL and firmware; doctoral/masters/bachelors in EE/CE/CS or equivalent experience; ability to pass Microsoft Cloud Background Check.
JTAG, ARMDS, Lauterbach TRACE32, ATE, Linux, Windows, Microsoft Excel
1mo
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MTS Digital Engineering
Morrisville, North Carolina, United States
$58k-$108k/yr HybridFull Time
0+ YOEBS EE (2-3 years) or MS EE/CE (0-1 year). Strong digital RTL design experience with Verilog/SystemVerilog, STA/CDC/Lint/DFT/BIST tools, plus Python/Perl scripting and simulation/debug skills.
SystemVerilog, Verilog, Python, Perl, Static Timing Analysis (STA), LEC, CDC, RDC, Lint, DFT, BIST
1d
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Principal Silicon Design Subsystem Lead
Mountain View or Raleigh or Redmond
$143k-$275k/yr HybridFull Time
3+ YOEAdvanced degree in EE/CE/CS or equivalent experience, 3+ years technical engineering experience (minimum), experience leading IP/Subsystem work, UVM/C++ verification, Python/Perl scripting, formal verification experience preferred.
Universal Verification Methodology (UVM), Python, Perl, C++, RTL
2mo
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CPU Power and Thermal Management Architect
Santa Clara or San Diego or Austin or Raleigh
$199k-$298k/yr OnsiteFull Time
6+ YOEAdvanced CPU/SoC architecture expertise (boot, idle/active power, DVFS, thermal and limit management), strong SW/FW collaboration, excellent documentation and communication. Advanced degree preferred with significant industry experience.
RTL, APCI, PSCI