20 rtl engineer jobs at 14 companies in Wilton, CT
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RTL Design Engineer
New York City or Palo Alto or London
$205k-$285k/yr HybridFull Time
Production SystemVerilog RTL experience, verification with UVM/cocotb/formal, taped-out silicon, ASIC/SoC design background, simulation and timing collaboration experience.
SystemVerilog, UVM, cocotb, formal, Chipyard, OpenTitan, CVA6, RISC-V
2mo
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Senior FPGA Engineer
Chicago or New York City or London
$225k-$325k/yr OnsiteFull Time
3+ YOEBachelor's in Computer or Electrical Engineering, 3+ years FPGA/hardware engineering experience, RTL/Verilog expertise, FPGA design flow experience, knowledge of TCP/IP, strong autonomous and problem-solving skills.
Verilog, System Verilog, RTL, XILINX, ALTERA, TCP/IP, synthesis, place & route, static timing analysis
6d
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Hardware Design Engineer
Tempe or San Jose or San Francisco or New York City
$133k-$210k/yr OnsiteFull Time
4+ YOEBachelor's degree or equivalent in electrical or computer engineering, 4+ years in high-speed digital board design and FPGA/RTL development, US citizenship, Secret clearance eligibility, and up to 10% travel.
SystemVerilog, Verilog, VHDL, AMD Vivado, Intel Quartus, Synopsys Synplify, Mentor Xpedition, Cadence, Altium, HyperLynx, Python, TCL, Perl, ModelSim, Questa, Git, Claude Code, Copilot, DDR4, SERDES, UART, I2C, SPI, LVDS, FPGA, RTL, SoC, ADC, DAC, CI/CD, AI
2mo
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Staff Engineer, Digital ASIC Design (CONTRACT)
Burlington or New York
HybridContract
8+ YOEBS/MS/PhD in EE/CE; 8+ yrs in digital IC/ASIC/SoC; RTL ownership; SystemVerilog/Verilog; high-throughput datapaths; silicon constraints; SV/UVM; Python/cocotb; post-silicon bring-up.
SystemVerilog/Verilog, UVM, Python, cocotb, RTL, RTL verification, Fixed-point modeling
1w
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ML ASIC Design Engineer
Mountain View or New York City
$175k-$215k/yr HybridFull Time
5+ YOEBS in Computer Engineering or equivalent experience; 5+ years with SystemVerilog, ASIC RTL design, and microarchitecture; 3+ years designing high-performance CPU, GPU, or NPU cores; Python or C++.
SystemVerilog, Python, C++, Chisel, Scala
3w
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Electrical Engineer II
Danbury, Connecticut, United States
OnsiteFull Time
4+ YOEBachelor's degree in electrical or computer engineering, 4+ years of firmware or embedded systems experience, VHDL/Verilog/SystemVerilog, communication protocols, FPGA tools, and U.S. citizenship with DOD clearance eligibility.
AMD Xilinx Vivado, Vitis, ModelSim, Questa, Integrated Logic Analyzer (ILA), oscilloscopes, logic analyzers, debuggers, Git, Microsoft Office Suite, VHDL, Verilog, SystemVerilog, UART, SPI, I2C, CAN, USB, Ethernet, FPGA, RTL
1w
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PMTS Silicon Design Engineer
Fishkill, New York, United States
$175k-$250k/yr OnsiteFull Time
5+ YOEMaster’s in computer, electrical, or electronic engineering plus 5 years of experience, or bachelor’s plus 7 years. Requires Verilog RTL, processor architecture, ASIC implementation, verification, timing, power management, DFT/DFD, and Perl, Shell, or Tcl scripting.
Verilog, Perl, Shell, Tcl, CPU, SOC, ASIC, Design-for-Test (DFT), Design-for-Debug (DFD)
2w
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ASIC Engineer
New York City, New York, United States
$250k-$300k/yr OnsiteFull Time
4+ YOE4+ years RTL design and verification experience; ASIC design using Synopsys or Cadence flows; experience in front-end, back-end or verification; FPGA/ASIC familiarity; programming experience (Python, C++, Java, Haskell); willingness to learn OCaml.
Hardcaml, OCaml, Synopsys, Cadence, Python, C++, Java, Haskell
1mo
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Two Sigma Securities, Hardware Engineer
New York City, New York, United States
$165k-$300k/yr HybridFull Time
1+ YOEMinimum 1 year RTL design and verification experience, proficiency in SystemVerilog and Python, FPGA/ASIC knowledge, timing analysis, network protocol familiarity; C++ is a plus.
SystemVerilog, Python, FPGA, ASIC, C++
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FPGA Engineer – Intern (US)
New York or Miami
$5k-$6k/wk OnsiteInternship
Pursuing a Bachelor's, Master's or PhD in EE/CE or related field; experience with SystemVerilog or VHDL; knowledge of hardware architecture, RTL, simulation, validation, FPGA synthesis; strong communication and problem-solving skills.
SystemVerilog, VHDL, Python, C, Tcl, Bash
1w
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CPU Emulation Engineer, Silicon
Austin or Mountain View or Portland or Poughkeepsie
$163k-$236k/yr OnsiteFull Time
8+ YOEBachelor's degree or equivalent practical experience; 8 years with emulation or FPGA platforms; RTL design using Verilog or SystemVerilog; scripting with Python, Perl, TCL, or Makefiles.
Synopsys ZeBu, HAPS, Cadence Palladium, Protium, Siemens Veloce, Verilog, SystemVerilog, Python, Perl, TCL, Makefiles, Field-Programmable Gate Array (FPGA), Register-Transfer Level (RTL)
1mo
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Research Engineer, Chip Design RL (Reinforcement Learning)
San Francisco or New York City
$500k-$850k/yr HybridFull Time
Bachelor's or equivalent, expertise in ASIC/FPGA design and EDA tools, experience with RTL, verification (UVM, formal methods), physical design and tapeout experience; RL experience and tooling experience preferred.
EDA tools, UVM, formal methods, place-and-route
4w
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Senior Digital ASIC Design Engineer
Upton, New York, United States
$115k-$145k/yr OnsiteFull Time
7+ YOEBachelor's in EE/CE/applied physics, 7+ years digital ASIC design, SystemVerilog/Verilog RTL, CAD/EDA tool experience, strong timing/CDC/low-power knowledge, and collaboration with mixed-signal, verification, and firmware teams.
SystemVerilog, Verilog, Cadence, Synopsys, Siemens, AXI, AHB, APB, Wishbone, I2C, SPI, JTAG, Tcl, Python, Perl, Make, shell
1d
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ASIC Technical Leader - Product Quality & Productization (Hybrid)
San Jose or New York City
$214k-$310k/yr HybridFull Time
20+ YOE20+ years in silicon DFT, test, quality, and program management, including 5+ years in high-reliability hardware; ASIC lifecycle expertise, Synopsys tools, ATE testers, and an electrical or computer engineering degree.
JTAG, SCAN, BIST, RTL, Synopsys, Design Compiler, Tetramax, Spyglass, VCS, ATE, 93K, SPC, JMP, Python, SQL, ISO 9001
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