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VLSI RTL design engineer
Fort Collins or Austin
$106k-$183k/yr HybridFull Time
3+ YOEBS/MS in EE/CS/CSE with 3+ years hardware design experience; experience in Digital RTL design, Verilog HDL, SRAM/Coherent Cache/NOC, scripting; strong communication and problem-solving skills.
Verilog HDL
1w
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Digital Design RTL Engineer
Fort Collins or San Jose
$122k-$195k/yr OnsiteFull Time
8+ YOEProven SystemVerilog RTL development in advanced nodes, 8+ years SoC experience, BSEE required (MSEE/PhD preferred), experience with PPA optimization, CDC/RDC, low-power design, and high-speed memory/SerDes protocols.
SystemVerilog
2mo
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ASIC Engineer 2
Longmont, Colorado, United States
$143k-$176k/yr OnsiteFull Time
Define ASIC design/verification requirements; HDL/RTL, scripting; physical design basics; review requirements and collaborate with architects.
Perl, Python, C, Unix shell, Verilog, SystemVerilog, VHDL, RTL
2mo
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Verification Engineer
San Jose or Fort Collins
$120k-$192k/yr OnsiteFull Time
8+ YOEBS in Electrical/Electronic Eng or CS; 8+ years ASIC/RTL verification; SystemVerilog/UVM/OVM; Python/C++; block- and system-level verification; strong debugging and collaboration.
SystemVerilog, UVM, OVM, Python, C/C++, RTL
1mo
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Senior FPGA Engineer - Control Systems
Boulder or Austin or Berkeley
$140k-$175k/yr OnsiteFull Time
Atom Computing: Building scalable quantum computers using arrays of neutral atoms.
5+ YOESenior FPGA engineer with 5+ years in FPGA/digital design; BS in EE/Physics or related field; strong SystemVerilog, RTL, Xilinx Vivado, Zynq, C/C++, Python; Linux experience; willing to learn quantum concepts.
RTL, SystemVerilog, VHDL, Vivado, Xilinx Zynq, Git, Yocto, C, C++, Python, Linux, Prototyping
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Principal ASIC Design Engineer
Boulder or Austin
$180k-$220k/yr HybridFull Time
Atom Computing: Building scalable quantum computers using arrays of neutral atoms.
10+ YOEMS/PhD in EE, 10+ years post-degree hardware experience, 2+ full ASIC design cycles, FPGA-to-ASIC experience, SystemVerilog/RTL proficiency, DSP RTL experience, knowledge of Cadence/Synopsys/Siemens EDA, mixed-signal background, mentoring experience.
RTL, SystemVerilog, Cadence, Synopsys, Siemens EDA, FPGA
2mo
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Design Verification (DV) Engineer
Austin or Boulder or Chicago or London or New York City
$175k-$250k/yr OnsiteFull Time
2+ YOE2+ years RTL verification for FPGA/ASIC; SystemVerilog/UVM; Python; Linux; Verilator; Cocotb; C++ is a plus.
SystemVerilog, UVM, Python, Verilator, Cocotb, Linux, C++
2mo
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ASIC Engineer 2
Longmont, Colorado, United States
$143k-$176k/yr OnsiteFull Time
Experience with Perl/Python/C/shell scripting, Verilog/System Verilog/VHDL, RTL design and verification, and physical design (layout, timing, power). Master's in ECE or related accepted.
Perl, Python, C, Unix shell, Verilog, System Verilog, VHDL
1mo
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CPU Cores Validation Senior Staff Engineer
Fort Collins, Colorado, United States
$178k-$268k/yr HybridFull Time
Experienced silicon validation engineer with strong programming (x86 assembly, C/C++, Perl, Ruby, Python), HDL knowledge (Verilog/System Verilog), DFT/JTAG familiarity, lab validation experience, and BS/MS in EE/CS/CSE.
x86 assembly, C, C++, Perl, Ruby, Python, Verilog HDL, System Verilog, JTAG -1149.x, BIST, LSSD/MuxD, RTL, DFT
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FPGA DSP Engineer
Fort Collins, Colorado, United States
$143k-$191k/yr OnsiteFull Time
12+ YOEBachelor's in EE/CE or related; 12+ years FPGA design experience; expert in RTL (SystemVerilog/VHDL), Xilinx toolchains (Vivado/Quartus), DSP implementation on FPGAs; FPGA verification and timing closure experience; eligible for U.S. Secret clearance.
SystemVerilog, VHDL, Vivado, Quartus, MATLAB, Git, Xilinx
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Senior Microprocessor VLSI Physical Design Engineer
Fort Collins, Colorado, United States
$156k-$268k/yr OnsiteFull Time
Experienced VLSI physical design engineer with hands-on high-speed design, chip floorplanning, CTS, P&R, STA, parasitic extraction, IR drop/EM analysis, Verilog RTL comprehension, scripting (Perl, C, tcl), and use of AI agents; BS/MS in EE/CS/CSE preferred.
Verilog, Perl, C, tcl, AI Agents
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Microprocessor VLSI Physical Design Engineer
Fort Collins, Colorado, United States
$127k-$217k/yr HybridFull Time
5+ YOE5+ years hardware design experience; BS/MS in EE, CS or CSE; hands-on high-speed VLSI design, digital circuits, Verilog RTL comprehension; familiarity with floorplanning, CTS, STA, IR drop, parasitics; programming in Perl, C, Tcl; strong analytical and communication skills.
Perl, C, Tcl, Verilog
2mo
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Solutions Architect
San Jose or Longmont
$203k-$348k/yr HybridFull Time
Experienced in FPGA/RTL, embedded systems, PCIe, DDR, Ethernet; strong C/C++, SystemVerilog.
SystemVerilog, Verilog, PCIe, CXL, DDR, Ethernet, AXI, Python, Tcl, Makefiles, Shell scripting, Linux kernel, IPC, RTOS, UVM, Palladium, Protium, Zebu