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CPU RTL Design Engineer
Austin or Phoenix
$142k-$269k/yr HybridFull Time
5+ YOEDegree in EE/CE/CS with significant experience (typical 5+ yrs); 7+ yrs RTL design with Verilog/V2K/SystemVerilog; low-power, CDC, static timing, UPF knowledge; scripting with TCL/Perl/Python; strong communication.
Verilog, V2K, System Verilog, TCL, Perl, Python, UPF, x86 assembly
1w
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Director, Digital Design & Verification
Chandler, Arizona, United States
OnsiteFull Time
Proven leader in digital IC design and verification for mixed-signal SoCs with expertise in RTL, verification methodologies (UVM, formal, AMS/DMS), architecture, and team building.
SystemVerilog, UVM, Formal, AMS/DMS, RTL, STA, DFT
1w
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Senior Technical Staff Engineer - Verification
Bangalore or Chandler
OnsiteFull Time
15+ YOE15+ years functional verification experience; expertise in SystemVerilog, UVM, formal methods, RTL and SoC verification; BS/MS in EE/CE or related; strong communication, mentoring, and problem-solving skills.
SystemVerilog, UVM, Formal, RTL, AI/ML
1mo
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Principal Engineer Electrical
Gilbert, Arizona, United States
$98k-$148k/yr OnsiteFull Time
5+ YOEBachelor's in STEM +5 years (or Master's +3 / PhD +1) experience in RTL/HDL FPGA/ASIC design for aerospace/space, proficiency in FPGA design flow, verification, synthesis, timing and power analysis; strong communication and problem solving.
HDL, RTL, Xilinx ISE/Vivado, Mentor Graphics ModelSim/QuestaSim, Synplify, System Verilog, Universal Verification Methodology (UVM), Signal Generators, Logic Analyzers, Digital Oscilloscopes, Embedded FPGA Debugging tools
2mo
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FPGA Engineer (AZ, Phoenix)
Phoenix, Arizona, United States
OnsiteFull Time
EndoSec: Security software and cryptographic hardware for government and defense.
Design, develop, test, and maintain FPGA IP cores and hardware security systems; RTL, C/C++, Python, VHDL/Verilog; FPGA tools; security clearance.
VHDL, Verilog, SystemVerilog, Python, C, C++, Tcl, Vivado, Questa, GHDL, Quartus Prime, Xilinx, Versal, AcE, AXI, Avalon
2mo
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FPGA Engineer (Space)
Tempe, Arizona, United States
$133k-$210k/yr OnsiteFull Time
6+ YOEBachelor's in Electrical/Computer Engineering; 6+ years FPGA design; SystemVerilog/VHDL; RTL design; lab/test experience; US citizenship; travel up to 10%
Verilog, SystemVerilog, VHDL, Xilinx Vivado, Quartus, Synplify, MATLAB
3w
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Senior DfT Engineer
Chandler, Arizona, United States
HybridFull Time
3+ YOEMaster's (MSEE) in relevant fields, 3+ years DfT/digital design experience, strong RTL coding and verification skills, Verilog/SystemVerilog proficiency, problem solving and communication skills.
Verilog, SystemVerilog
2mo
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Staff Engineer, Design Verification Engineering
Chandler, Arizona, United States
$172k-$199k/yr HybridFull Time
4+ YOEMaster's degree in Electrical Engineering, Materials Engineering, or Physics with 4 years in design verification; or Bachelor's with 6 years; strong SystemVerilog/UVM skills; Verilog-RTL, mixed-signal verification; Xcelium/VCS; scripting (Perl/Python/C).
SystemVerilog, UVM, Verilog-AMS, Cadence AMS, Xcelium, VCS, Perl, Python, C
3d
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Hardware Designer
Phoenix or United States
RemoteFull Time
5+ YOE5+ years electronics design experience, Bachelors in Electrical/Computer Engineering, high-speed PCB and system design expertise, familiarity with FPGA and signal integrity, bench bring-up and test experience.
LTSpice, OrCAD Capture CIS, Cadence CIS, Cadence Allegro, Verilog, RTL, HLS, optical test set, signal analyzer, oscilloscope, VNA, signal generator