2mo
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Electrical Engineer II ASIC/FPGA Verification (Onsite)
El Segundo, California, United States
$76k-$144k/yr OnsiteFull Time
2+ YOEDegree in STEM and at least 2 years of relevant experience; active SECRET security clearance; RTL/VHDL/Verilog experience; testbench development; familiarity with ASIC/FPGA verification.
SystemVerilog, OVM/UVM, VHDL, Verilog, Questasim, Synplify, Quartus, Vivado, C++, Perl, Git, Subversion
5d
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Principal Engineer ASIC or Sr Principal Engineer ASIC
Manhattan Beach, California, United States
$125k-$235k/yr OnsiteFull Time
5+ YOESTEM degree with relevant years of experience, RTL design (VHDL/Verilog/SystemVerilog), ASIC/FPGA architecture, verification experience, lab testing, and ability to obtain a government security clearance.
VHDL, Verilog, SystemVerilog, Xilinx Vivado, Microchip Libero, UVM
5d
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R&D Software Engineering Internship
Calabasas or Santa Clara
$33-$35/hr OnsiteInternship
0+ YOEBachelor's or Master's in EE/CE or related, strong digital design and FPGA experience (RTL, simulation, synthesis), familiarity with VHDL/Verilog/SystemVerilog, strong problem-solving and communication skills.
VHDL, Verilog, SystemVerilog, PCIe, Ethernet, SerDes, FPGA
1mo
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FPGA Engineer
El Segundo or Los Angeles or Washington or San Francisco or Seattle or London
$160k-$225k/yr OnsiteFull Time
5+ YOEBachelor's in a relevant field, 5+ years FPGA RTL design experience, Verilog/SystemVerilog, AXI protocols, Vivado and SoC FPGA experience, Bash/Python scripting, U.S. Person required.
Verilog, SystemVerilog, AXI4, AXI4-Lite, AXI4-Stream, Vivado Design Suite, Zynq, Ultrascale, Ultrascale+, Versal, TCP, UDP, IP, I2C, JTAG, UART, SPI, CAN, Bash, Python, Simulink, MATLAB, C, C++, SystemC, Chisel, VHDL, git, Bitbucket CI, Jenkins
1mo
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Principal Engineer Pre-Silicon Digital Verification
Andover or Austin or El Segundo
$146k-$201k/yr HybridFull Time
Experience in ASIC design and digital/mixed-signal verification, test plan and testbench development, SystemVerilog/UVM, RTL and functional coverage, formal verification, and scripting (Unix/Linux shell, Perl, Python).
SystemVerilog, UVM, Unix/Linux shell, Perl, Python
1mo
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Sr. FPGA Engineer
El Segundo or Los Angeles or Hawthorne
$160k-$225k/yr OnsiteFull Time
5+ YOEB.S. in engineering or CS, 5+ years FPGA/RTL experience, Verilog/SystemVerilog, Vivado toolchain, AXI protocols, ARM/SoC FPGA experience, Python/Bash scripting, U.S. Person status required.
Verilog, SystemVerilog, ARM AMBA AXI Protocol (AXI4, AXI4-Lite, AXI4-Stream), Vivado Design Suite, Zynq, Ultrascale, Ultrascale+, Versal, TCP/UDP/IP, I2C, JTAG, UART, SPI, CAN, Bash, Python, Simulink, MATLAB, C, C++, SystemC, Chisel, VHDL, git, Bitbucket CI, Jenkins, NTP, PTP, Ettus, NI, HackRF, HLS Synthesis, GPU
1mo
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Regional Vice President, Sales - West Coast
Thousand Oaks or California
$200k-$250k/yr RemoteFull Time
5+ YOE3+ Mgmt5+ years in real estate finance or mortgage banking; 3+ years managing sales teams; proven RTL/DSCR/construction/investor lending experience; CRM and sales analytics proficiency; Bachelor’s preferred.
1mo
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Firmware Engineer
El Segundo or Los Angeles or Washington or San Francisco or Seattle or London
$160k-$225k/yr OnsiteFull Time
5+ YOEBachelor's in CE/EE/CS, 5+ years FPGA RTL design experience, Verilog/SystemVerilog, AXI protocols, Vivado/SoC FPGAs, TCP/UDP/IP and serial protocols, Bash/Python scripting; U.S. Person required.
Verilog, SystemVerilog, Vivado Design Suite, Simulink, MATLAB, C, C++, SystemC, Chisel, VHDL, Bash, Python, git, Bitbucket CI, Jenkins
1mo
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Senior ASIC/FPGA Verification Engineer (Onsite)
El Segundo or Fullerton
$96k-$182k/yr OnsiteFull Time
5+ YOEActive transferable U.S. SECRET clearance and U.S. citizenship, STEM degree (BS or advanced) with 5+ years (BS) or 3+ years (advanced) experience, RTL verification using VHDL/Verilog/SystemVerilog, testbench and coverage, and revision control (Git/Subversion).
SystemVerilog, OVM, UVM, VHDL, Verilog, Git, Subversion, QuestaSim, Synplify, Quartus, Vivado, Unix, Linux
1w
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Principal ASIC/FPGA Verification Engineer (Onsite)
El Segundo or Fullerton
$118k-$225k/yr OnsiteFull Time
8+ YOEU.S. citizen with active transferable Secret clearance, STEM degree with 8+ years (or advanced degree with 5+ years), 4+ years RTL/SystemVerilog/VHDL/Verilog verification, testbench and coverage development, mentoring experience, and familiarity with Git/Subversion and simulation tools.
SystemVerilog, OVM, UVM, VHDL, Verilog, Git, Subversion, Unix/Linux, C, C++, Python, Perl, shell, QuestaSim, Synplify, Quartus, Vivado
1mo
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Research Scientist
San Jose or Santa Barbara
$150k-$350k/yr OnsiteFull Time
Degree in CS/ML/EE or equivalent research experience; deep expertise in large language models, deep learning and AI agent architectures; experience with large-scale model training and productionizing research; strong Python and ML framework skills.
PyTorch, JAX, Python, Electronic Design Automation (EDA), RTL, LLMs