48 rtl jobs at 20 companies in South Gate, CA
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Sr. RTL Design Engineer (Silicon Engineering)
Austin or Irvine or Redmond or Sunnyvale
$170k-$235k/yr OnsiteFull Time
5+ YOEBachelor’s in electrical/computer engineering or computer science; 5+ years of RTL implementation experience.
Verilog, SystemVerilog, Python, EDA tools, HDL simulators, HDL Lint
2mo
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Principal FPGA / RTL Design Engineer - Signal Processing
Los Angeles or Irvine
$175k-$225k/yr HybridFull Time
10+ YOEBS in ECE/CS or related; 10+ yrs RTL/FPGA design or 6+ yrs with PhD; Xilinx FPGAs, Vivado; fixed-point DSP; US person.
Xilinx FPGAs, Vivado IDE, Fixed-point arithmetic, Digital Signal Processing, MATLAB, Python, Perl
2mo
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FPGA Design Engineer
Los Angeles or Irvine
$100k-$140k/yr HybridFull Time
6+ YOESenior FPGA design expert with 6+ years (MS: 4y; PhD: 2y) in fixed-point DSP, multiple clock-domain FPGA designs, Xilinx Vivado.
Xilinx FPGA, Vivado, MATLAB, HDL, FPGA design, RTL coding
2mo
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Senior Avionics FPGA Design & Verification Engineer - TeraWave
Seattle or Los Angeles or Denver
$157k-$220k/yr OnsiteFull Time
Blue Origin: Develops reusable rockets and systems for human spaceflight.
7+ YOE7+ years in digital design/SoC architecture; SystemVerilog/Verilog RTL; FPGA/SoC integration; timing and bus protocols; RTL simulation and debugging; hardware design verification.
SystemVerilog, Verilog, QuestaSim, FPGA, SoC, RTL, AXI, AHB
5d
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Field Application Engineer – PowerPro
Austin or Costa Mesa or San Diego or Santa Clara
$147k-$293k/yr HybridFull Time
3+ YOE3+ years RTL design experience with Verilog/SystemVerilog/VHDL, RTL power analysis knowledge, scripting with Tcl/Python, BS/MS in EE/CS or related, strong communication and customer-facing skills.
PowerPro, Verilog, SystemVerilog, VHDL, Tcl, Python, PrimePower, PowerArtist, UPF, CPF
2mo
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Senior Digital Engineer
Sydney or Sydney or Irvine or Boston or Bangalore or Cambridge or Hangzhou or Taipei or Tokyo or Sydney
OnsiteFull Time
5+ YOE5+ years as Senior Digital Engineer; strong Verilog/SystemVerilog; RTL design; low-power techniques; collaborate with firmware/PHY teams.
Verilog/SystemVerilog, C, Python, Tcl, Shell, Makefiles, UPF/CPF, Scripting and automation
21h
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R&D Software Engineering Internship
Calabasas or Santa Clara
$40-$43/hr OnsiteInternship
Bachelor’s or Master’s in EE/CE or related, strong FPGA development experience (RTL, simulation, synthesis, debug), exposure to VHDL/Verilog/SystemVerilog, and strong analytical and communication skills.
VHDL, Verilog, SystemVerilog, PCIe, Ethernet, SerDes
6d
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Senior Applications Engineer - Emulation
San Diego or Costa Mesa or Austin or Wilsonville
$147k-$293k/yr HybridFull Time
4+ YOE4+ years in design/verification/emulation, BS/MS in EE/CE/CS, experience with emulation platforms, RTL/verification languages, scripting, strong communication and demo skills.
Veloce, Palladium, Zebu, SystemVerilog, Verilog, VHDL, SystemC, C/C++, Perl, Python, XML, JSON, Makefiles, shell scripts
2mo
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Electrical Engineer II ASIC/FPGA Verification (Onsite)
El Segundo, California, United States
$76k-$144k/yr OnsiteFull Time
2+ YOEDegree in STEM and at least 2 years of relevant experience; active SECRET security clearance; RTL/VHDL/Verilog experience; testbench development; familiarity with ASIC/FPGA verification.
SystemVerilog, OVM/UVM, VHDL, Verilog, Questasim, Synplify, Quartus, Vivado, C++, Perl, Git, Subversion
1w
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Principal Engineer ASIC or Sr Principal Engineer ASIC
Manhattan Beach, California, United States
$125k-$235k/yr OnsiteFull Time
5+ YOESTEM degree with relevant years of experience, RTL design (VHDL/Verilog/SystemVerilog), ASIC/FPGA architecture, verification experience, lab testing, and ability to obtain a government security clearance.
VHDL, Verilog, SystemVerilog, Xilinx Vivado, Microchip Libero, UVM
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Associate ASIC/FPGA Design or Verification Engineer
El Segundo or Huntington Beach or Fairfax
$99k-$133k/yr OnsiteFull Time
2+ YOEUS citizenship with ability to obtain U.S. Secret clearance, Bachelor\u0000s degree in a relevant field, experience with ASIC/FPGA design or verification, and RTL experience with Verilog/VHDL/SystemVerilog.
Verilog, VHDL, SystemVerilog, System Verilog Assertions, UVM, Palladium, Make, Perl, Python, svn, cvs, git, Linux, ARM, JESD204C, PCIe, Ethernet
1mo
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FPGA Engineer
El Segundo or Los Angeles or Washington or San Francisco or Seattle or London
$160k-$225k/yr OnsiteFull Time
5+ YOEBachelor's in a relevant field, 5+ years FPGA RTL design experience, Verilog/SystemVerilog, AXI protocols, Vivado and SoC FPGA experience, Bash/Python scripting, U.S. Person required.
Verilog, SystemVerilog, AXI4, AXI4-Lite, AXI4-Stream, Vivado Design Suite, Zynq, Ultrascale, Ultrascale+, Versal, TCP, UDP, IP, I2C, JTAG, UART, SPI, CAN, Bash, Python, Simulink, MATLAB, C, C++, SystemC, Chisel, VHDL, git, Bitbucket CI, Jenkins
1mo
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Senior Principal Digital Design Engineer
Irvine, California, United States
$186k-$228k/yr OnsiteFull Time
6+ YOEExpert digital ASIC design experience, SystemVerilog/RTL implementation, block/system verification, synthesis/power/timing analysis, and technical leadership; BS in EE (or advanced) plus extensive experience.
SystemVerilog, Verilog, UVM, SystemC, PCIe, PCI-SIG, IEEE 802.3, SDC
1d
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Design Verification Engineer
Broomfield or San Diego or Fort Collins or San Jose or Irvine
$144k-$230k/yr OnsiteFull Time
10+ YOE12+ years verification experience for complex digital and mixed-signal circuits; proficiency with SystemVerilog/UVM/SVA, scripting, simulation tools, and RTL/gate-level debug; BS/MS in EE/CE.
SystemVerilog, UVM, SVA, Synopsys, Cadence, Mentor, Perl, Python, Tcl, DesignSync, git, Palladium, Veloce, Zebu, Xilinx, ICL, PDL, Tessent
1d
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Senior ASIC Emulation Engineer
Los Angeles or United States
$170k-$250k/yr OnsiteFull Time
5+ YOE5+ years ASIC/SoC emulation experience, SystemVerilog and RTL knowledge, hands-on with Palladium/ZeBu/Veloce, scripting (Python/Perl/TCL), C/C++ firmware experience, and cross-functional debug skills.
Palladium, ZeBu, Veloce, SystemVerilog, Python, Perl, TCL, C, C++, APB, AHB, AXI, JTAG, SPI, HAPS, Protium, PCIe, Ethernet, USB, SERDES
1w
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Principal Engineer ASIC or Sr Principal Engineer ASIC
Manhattan Beach, California, United States
$125k-$235k/yr OnsiteFull Time
5+ YOESTEM degree with 3–8+ years experience, RTL design (VHDL/Verilog) for space, ASIC/FPGA architecture, verification (SystemVerilog/UVM), lab testing, and ability to obtain/maintain government security clearance.
VHDL, Verilog, Xilinx Vivado, Microchip Libero, SystemVerilog, UVM, DSP
1mo
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Regional Vice President, Sales - West Coast
Thousand Oaks or California
$200k-$250k/yr RemoteFull Time
5+ YOE3+ Mgmt5+ years in real estate finance or mortgage banking; 3+ years managing sales teams; proven RTL/DSCR/construction/investor lending experience; CRM and sales analytics proficiency; Bachelor’s preferred.
1mo
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Senior FPGA Engineer
Long Beach, California, United States
$148k-$222k/yr OnsiteFull Time
5+ YOEBachelors in EE/Computer Eng or related; 5+ years FPGA development and high-speed digital systems experience in mission-critical applications; RTL/verification/synthesis/timing expertise; cross-functional collaboration skills.
VHDL, Verilog, SystemVerilog, SpinalHDL, Chisel, Vitis, SystemC, Simulink, RISC-V, AMD Xilinx, Intel, Microchip, CI/CD
3w
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Principal, IC Digital Design Engineer
Irvine, California, United States
$151k-$223k/yr OnsiteFull Time
12+ YOE12+ years ASIC digital design experience, RTL implementation (SystemVerilog), DSP and high-speed datapath expertise, familiarity with front-end flows (lint, CDC/RDC, synthesis, STA), strong debug and leadership skills.
SystemVerilog, lint, CDC, RDC, synthesis, STA, PNR, emulation, FPGA
2mo
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Staff FPGA Design Engineer
Irvine, California, United States
$150k-$190k/yr OnsiteFull Time
8+ YOEBachelor's in EE/CE, 8+ years FPGA RTL architecture/development/verification, strong SystemVerilog or VHDL skills, experience with Microship Polarfire/AMD Zynq/Versal/Ultrascale, verification methodologies, Git, Python/Tcl/Bash, C/C++ on Linux, and eligibility for DoD security clearance.
SystemVerilog, VHDL, Microship Polarfire, AMD Zynq US+, Versal, AMD Ultrascale, Vivado, Mentor Modelsim/Questasim, AXI, PCIe, DDR4, DDR5, JESD204B, JESD204C, 100Gb ethernet, SPI, I2C, UART, CAN FD, LVDS, Git, Python, Tcl, Bash, Linux, C/C++
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