3mo
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Design Verification (DV) Engineer
Austin or Boulder or Chicago or London or New York City
$175k-$250k/yr OnsiteFull Time
2+ YOE2+ years RTL verification for FPGA/ASIC; SystemVerilog/UVM; Python; Linux; Verilator; Cocotb; C++ is a plus.
SystemVerilog, UVM, Python, Verilator, Cocotb, Linux, C++
1mo
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Hardware Engineer
Chicago, Illinois, United States
$200k-$225k/yr OnsiteFull Time
BS in EE/CE/CS or related, strong RTL design using SystemVerilog, C++ experience, verification and multi-clock-domain knowledge, Ethernet fundamentals, Python/Bash scripting, and strong debugging and collaboration skills.
SystemVerilog, C++, Python, Bash, FPGA, PMA (Physical Media Attachment), Ethernet, RTL
2mo
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FPGA Engineer (IL, Schaumburg)
Schaumburg, Illinois, United States
OnsiteFull Time
EndoSec: Security software and cryptographic hardware for government and defense.
Experience with RTL, C/C++, Python, VHDL/Verilog; hardware security; FPGA design and verification; system integration; cryptography concepts.
C/C++, Python, VHDL, Verilog, Tcl, Vivado, Questa, Quartus Prime, GHDL, Xilinx, Versal, Agilex, AXI, Avalon, cocotb, pyuvm