3w
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RTL Design/AMS Verification Engineer
Richardson, Texas, United States
RemoteFull Time
5+ YOE5+ years IC design experience; Verilog RTL design and verification experience; Cadence/Synopsys flows; AMS simulation, synthesis and APR; Bachelor's degree in Electrical Engineering; US work authorization (ITAR) required.
Verilog, Cadence, Synopsys, Python, Perl, Tcl, SKILL
3mo
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Sr. RTL Engineer
Orlando, Florida, United States
OnsiteFull Time
5+ YOESenior FPGA/RTL engineer with SystemVerilog, FPGA design, modeling, simulation, verification, and test; knowledge of DSP, firmware, and hardware integration.
SystemVerilog, Verilog, Python, FPGA design, HDL Synthesis, VCS, Synplify, Git, Jira
3mo
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RTL Design Engineer
Cupertino or United States
OnsiteFull Time
Bachelor's degree in Electrical Engineering; experience in RTL design, Verilog/SystemVerilog, DSP concepts, and circuit verification.
Verilog, SystemVerilog, linting tools, clock-domain crossing checkers, Synthesis, Static Timing Analysis, Design-for-Test, Scripting (Perl, Python), Formal verification, DSP concepts, hardware optimization
2mo
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Verification Engineer
San Jose or Fort Collins
$120k-$192k/yr OnsiteFull Time
8+ YOEBS in Electrical/Electronic Eng or CS; 8+ years ASIC/RTL verification; SystemVerilog/UVM/OVM; Python/C++; block- and system-level verification; strong debugging and collaboration.
SystemVerilog, UVM, OVM, Python, C/C++, RTL
2w
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RTL Design Engineer
San Jose, California, United States
HybridFull Time
Experience in RTL digital design and verification, Verilog/System Verilog, scripting (Perl/Tcl/Python), FPGA/SoC design concepts, and strong analytical and communication skills; Bachelor’s or Master’s in Computer or Electrical Engineering.
Verilog, System Verilog, Perl, Tcl, Python
3w
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RTL Design Engineer
New York City or Palo Alto or London
$205k-$285k/yr HybridFull Time
Production SystemVerilog RTL experience, verification with UVM/cocotb/formal, taped-out silicon, ASIC/SoC design background, simulation and timing collaboration experience.
SystemVerilog, UVM, cocotb, formal, Chipyard, OpenTitan, CVA6, RISC-V
3mo
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ASIC Verification Engineer
Austin, Texas, United States
$116k-$190k/yr HybridFull Time
2+ YOEBS/MS in Electrical or Computer Engineering; 2+ years ASIC/RTL verification; pre-silicon verification (UVM, SystemVerilog); RTL verification; Perl/Python; debugging; exposure to verification tools; strong communication.
UVM, SystemVerilog, Perl, Python, dc_shell, VCS, GDB, Debussy
6d
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Senior CPU RTL Engineer
Santa Clara, California, United States
$142k-$213k/yr OnsiteFull Time
Planning and performing CPU RTL development, microarchitecture and performance exploration, RTL design targeting power/performance/area/timing, and collaborating on verification and physical implementation. Master's degree in EE/CE/CS accepted.
1w
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TPU RTL Design Engineer
Sunnyvale, California, United States
$138k-$198k/yr OnsiteFull Time
2+ YOEBachelor's degree or equivalent,2+ years ASIC RTL design experience focused on clocking/reset/timing-critical RTL,SystemVerilog and scripting (Python/Tcl/Perl) proficiency,experience with clock control and verification.
SystemVerilog, Python, Tcl, Perl
3mo
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FPGA Verification Engineer - Avionics
Saratoga, California, United States
$150k-$250k/yr OnsiteFull Time
4+ YOE4+ years FPGA/ASIC verification; SystemVerilog/UVM; develop verification environments; RTL simulation; functional coverage; timing analysis.
SystemVerilog, UVM, RTL simulators, VCS, QuestaSim, Python, TCL, lint, CDC analysis tools
3w
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Senior Firmware Verification Engineer
Austin, Texas, United States
OnsiteFull Time
5+ YOEBS/MS in EE or Computer Engineering required; 5+ years firmware verification experience in pre-silicon; SystemVerilog, C, Python/Perl skills; familiarity with RTL, emulation, and lab test equipment.
SystemVerilog, UVM, C, Python, Perl, RTL, FPGA, QEMU, SimVision, Verdi, oscilloscopes, power supplies, logic analyzers
1mo
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Staff Design Verification Engineer, HBM Architecture
Richardson, Texas, United States
OnsiteFull Time
7+ YOEBachelor's in EE/CE, 7+ years verification engineering experience (including 5+ years in digital/analog/mixed-signal), 4+ years custom or RTL verification, strong communication and independent verification strategy skills.
Verilog, FastSpice, GenAI, RTL
1d
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ASIC SoC Verification Engineer (788438)
Austin, Texas, United States
HybridFull Time
Experience in SoC/IP/SubSystem verification, SystemC/TLM and RTL environments, hardware emulation, knowledge of high-speed interfaces, strong problem-solving and communication;BS required, MS preferred.
SystemC/TLM, RTL, hardware emulation
1d
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ASIC SoC Verification Engineer
Austin, Texas, United States
OnsiteFull Time
Experience in SoC/IP/Subsystem verification, SystemC/TLM and RTL verification, hardware emulation familiarity, strong problem-solving and communication; BS required (MS preferred).
SystemC, TLM, RTL, hardware emulation
6d
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IP Design Verification Engineer
Santa Clara, California, United States
$164k-$269k/yr HybridFull Time
6+ YOEBachelor's degree or equivalent with 6+ years (less with advanced degree), proficiency in System Verilog and RTL, testbench and verification environment experience, strong debugging and problem-solving skills.
System Verilog, RTL
1mo
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Formal Verification Engineer
San Jose, California, United States
$150k-$350k/yr OnsiteFull Time
Deep formal verification expertise, experience with assertion-based verification and proof debugging, proficiency scripting in Python or Tcl, and hands-on use of formal EDA tools to verify RTL and production IP.
JasperGold, VC Formal, Questa Formal, SystemVerilog Assertions (SVA), Python, Tcl
3mo
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Sr/Staff Design Verification Engineer, HBM Verification Architecture
Richardson, Texas, United States
OnsiteFull Time
4+ YOEBachelor's in EE/CE, 4+ years verification engineering experience (digital/analog/mixed-signal), 2+ years in custom or RTL verification flows, strong debug and communication skills, EM/SoC verification experience preferred.
Verilog, FastSpice, RTL2GDS, GenAI
2mo
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ASIC Verification Engineer
San Jose, California, United States
OnsiteFull Time
8+ YOE8+ years in UVM verification; RTL/gate-level verification; test plan and testbench development in C/Assembly/SystemVerilog; AMBA AXI/AHB/APB; PCIe/USB/Ethernet; scripting; repository and bug-tracking tools.
UVM, SystemVerilog, C, Assembly, Python, Shell, Perl, AMBA AXI, AHB, APB, PCIe, USB, Ethernet, DDR3/4, LPDDR, I2C/I3C, SPI, SD/SDIO/eMMC, UART, Git, JIRA, Bitbucket, Jenkins
2mo
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SLD FPGA Verification Engineer III - Lunar Permanence
Seattle or Space Coast
$131k-$183k/yr OnsiteFull Time
Blue Origin: Develops reusable rockets and systems for human spaceflight.
5+ YOEBS/MS in Electrical or Computer Engineering; 5+ years FPGA/ASIC verification; RTL simulation tools; UVM; testbench development; DO-254 knowledge a plus.
QuestaSim, ModelSim, SystemVerilog, UVM, RTL, DO-254
1mo
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Senior ASIC Verification Engineer
Austin, Texas, United States
$136k-$265k/yr OnsiteFull Time
3+ YOE3+ years relevant experience, Bachelor's/Master's in Computer or Electrical Engineering (or equivalent), proficiency in System Verilog, UVM, Python, Verilog, RTL, and familiarity with VCS and Verdi.
System Verilog, UVM, Python, Verilog, RTL, VCS, Verdi
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