9 rtl verification engineer jobs at 4 companies in Colorado
2mo
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Verification Engineer
San Jose or Fort Collins
$120k-$192k/yr OnsiteFull Time
8+ YOEBS in Electrical/Electronic Eng or CS; 8+ years ASIC/RTL verification; SystemVerilog/UVM/OVM; Python/C++; block- and system-level verification; strong debugging and collaboration.
SystemVerilog, UVM, OVM, Python, C/C++, RTL
3d
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Design Verification Engineer
Broomfield or San Diego or Fort Collins or San Jose or Irvine
$144k-$230k/yr OnsiteFull Time
10+ YOE12+ years verification experience for complex digital and mixed-signal circuits; proficiency with SystemVerilog/UVM/SVA, scripting, simulation tools, and RTL/gate-level debug; BS/MS in EE/CE.
SystemVerilog, UVM, SVA, Synopsys, Cadence, Mentor, Perl, Python, Tcl, DesignSync, git, Palladium, Veloce, Zebu, Xilinx, ICL, PDL, Tessent
2mo
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Senior Avionics FPGA Design & Verification Engineer - TeraWave
Seattle or Los Angeles or Denver
$157k-$220k/yr OnsiteFull Time
Blue Origin: Develops reusable rockets and systems for human spaceflight.
7+ YOE7+ years in digital design/SoC architecture; SystemVerilog/Verilog RTL; FPGA/SoC integration; timing and bus protocols; RTL simulation and debugging; hardware design verification.
SystemVerilog, Verilog, QuestaSim, FPGA, SoC, RTL, AXI, AHB
4d
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Senior Avionics FPGA Design & Verification Engineer - TeraWave
Seattle or Los Angeles or Denver
$144k-$220k/yr OnsiteFull Time
Blue Origin: Develops reusable rockets and systems for human spaceflight.
7+ YOEBS in EE/CE,7+ years digital design and SoC/FPGA experience,proficiency in SystemVerilog/Verilog,experience with SoC integration,timing knowledge,and simulation/debugging skills.
SystemVerilog, Verilog, Questasim, AXI, AHB, FPGA, SoC, RTL
2mo
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Senior Engineer, Digital Design Engineering
Colorado Springs, Colorado, United States
$112k-$167k/yr HybridFull Time
2+ YOEMaster's degree in Electrical or Electronic Engineering or Computer Science/Engineering; 2+ years in digital design/verification; RTL/Verilog/SystemVerilog expertise; Cadence or Synopsys tools.
Verilog, SystemVerilog, Cadence, Synopsys, RTL, Digital Design
1mo
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SLD Avionics FPGA Engineer III - Lunar Permanence
Seattle or Denver
$120k-$183k/yr OnsiteFull Time
Blue Origin: Develops reusable rockets and systems for human spaceflight.
5+ YOEBachelor's/Master's in engineering or related field,5+ years FPGA/ASIC design and verification,RTL in Verilog/SystemVerilog/VHDL,FPGA tools and simulators,UVM/OVM testbenches,ability to travel ~10%,U.S. work authorization required.
Verilog, SystemVerilog, VHDL, Xilinx Vivado, Intel Quartus, Lattice Diamond, Radiant, Microchip Libero, ModelSim, QuestaSim, Perl, Python, Tcl, Git, SVN, AMBA, AXI, AHB, APB, IEEE 802.3, XAUI, JESD204, I2C, SPI, UVM, OVM
1mo
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FPGA DSP Engineer
Fort Collins, Colorado, United States
$143k-$191k/yr OnsiteFull Time
12+ YOEBachelor's in EE/CE or related; 12+ years FPGA design experience; expert in RTL (SystemVerilog/VHDL), Xilinx toolchains (Vivado/Quartus), DSP implementation on FPGAs; FPGA verification and timing closure experience; eligible for U.S. Secret clearance.
SystemVerilog, VHDL, Vivado, Quartus, MATLAB, Git, Xilinx
3mo
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FPGA Engineer (CO, Colorado Springs)
Colorado Springs, Colorado, United States
OnsiteFull Time
EndoSec: Security software and cryptographic hardware for government and defense.
Design, develop, test, and maintain FPGA IP cores and FPGA-based hardware security systems; work with RTL/C/C++, Python, VHDL/Verilog; system integration and verification; travel up to 10%; requires ability to obtain/maintain U.S. Government security clearance.
C, C++, Python, VHDL, Verilog, Tcl, Vivado, GHDL, Questa, Quartus Prime, Xilinx, Versal, Stratix, Agilex, Zynq, AXI, ACE, Avalon, cocotb, pyuvm
3w
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Senior ASIC Digital / DSP Design Engineer
Colorado Springs, Colorado, United States
$142k-$236k/yr OnsiteFull Time
10+ YOEBS/MS in EE/CE,10+ years experience in digital/DSP/ASIC design and verification,RTL and DSP algorithm development,experience with ASIC/FPGA flows and verification,strong math and communication skills,US-person required.
Cadence, Mentor