5d
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Senior Technical Staff Engineer - Verification
Bangalore or Chandler
OnsiteFull Time
15+ YOE15+ years functional verification experience; expertise in SystemVerilog, UVM, formal methods, RTL and SoC verification; BS/MS in EE/CE or related; strong communication, mentoring, and problem-solving skills.
SystemVerilog, UVM, Formal, RTL, AI/ML
6d
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Director, Digital Design & Verification
Chandler, Arizona, United States
OnsiteFull Time
Proven leader in digital IC design and verification for mixed-signal SoCs with expertise in RTL, verification methodologies (UVM, formal, AMS/DMS), architecture, and team building.
SystemVerilog, UVM, Formal, AMS/DMS, RTL, STA, DFT
2mo
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Staff Engineer, Design Verification Engineering
Chandler, Arizona, United States
$172k-$199k/yr HybridFull Time
4+ YOEMaster's degree in Electrical Engineering, Materials Engineering, or Physics with 4 years in design verification; or Bachelor's with 6 years; strong SystemVerilog/UVM skills; Verilog-RTL, mixed-signal verification; Xcelium/VCS; scripting (Perl/Python/C).
SystemVerilog, UVM, Verilog-AMS, Cadence AMS, Xcelium, VCS, Perl, Python, C
4w
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Principal Engineer Electrical
Gilbert, Arizona, United States
$98k-$148k/yr OnsiteFull Time
5+ YOEBachelor's in STEM +5 years (or Master's +3 / PhD +1) experience in RTL/HDL FPGA/ASIC design for aerospace/space, proficiency in FPGA design flow, verification, synthesis, timing and power analysis; strong communication and problem solving.
HDL, RTL, Xilinx ISE/Vivado, Mentor Graphics ModelSim/QuestaSim, Synplify, System Verilog, Universal Verification Methodology (UVM), Signal Generators, Logic Analyzers, Digital Oscilloscopes, Embedded FPGA Debugging tools
3mo
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Senior Digital Design Engineer
Austin or Greensboro or Chandler
HybridFull Time
5+ YOESenior digital IC design with Verilog/RTL, 5+ years for Bachelors; 3+ for Masters; strong verification and SoC experience.
Verilog, UVM, MATLAB, Simulink
2w
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Senior DfT Engineer
Chandler, Arizona, United States
HybridFull Time
3+ YOEMaster's (MSEE) in relevant fields, 3+ years DfT/digital design experience, strong RTL coding and verification skills, Verilog/SystemVerilog proficiency, problem solving and communication skills.
Verilog, SystemVerilog
6d
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Senior Engineer I- Design
Chandler, Arizona, United States
OnsiteFull Time
5+ YOEBSEE with 5+ years experience, proficiency in Verilog/SystemVerilog and UVM, Python and TCL scripting, familiarity with Synopsys/Cadence/Siemens EDA tools, and experience with RTL design and verification.
Verilog, SystemVerilog, UVM, Python, TCL, Shell, Synopsys, Cadence, Siemens, AI/ML
3mo
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Senior Staff Digital Design Engineer
Austin or Greensboro or Chandler
HybridFull Time
10+ YOESenior-level digital IC design with deep Verilog/RTL experience; strong design, verification, and collaboration skills.
Verilog, UVM, MATLAB, Simulink
3w
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Physical Design Engineer
Massachusetts or Phoenix
$91k-$149k/yr OnsiteFull Time
0+ YOEDesign and implement physical IC/SoC from RTL to GDS, perform synthesis/place-and-route/CTS/STA, power and noise analysis, verification and optimization using EDA tools.
EDA tools, TCL
2mo
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Principal Engineer - Digital Design
Chandler, Arizona, United States
OnsiteFull Time
10+ YOEBachelors with 10+ years in digital design; RTL coding/verification; USB/Ethernet PHY knowledge; Verilog/SystemVerilog; UVM/VMM a plus; ASIC flow; CAD tools; timing; scripting.
Verilog, SystemVerilog, UVM, Questa, Design Compiler, Formality, Spyglass, Crossing Clock domain checking, lint, stuck-at, At-Speed scan, Scripting (C, TCL, Perl, Awk, UNIX shell), CVS, Perforce, DesignSync
3mo
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Principal FPGA/ASIC Engineer - Level 3
Gilbert, Arizona, United States
$79k-$119k/yr HybridFull Time
1+ YOEBachelor's in STEM with 5+ yrs FPGA design experience (or MS with 3+ yrs, PhD with 1+ yr); HDL/HDL verification, FPGA design flow, aerospace experience, and ability to obtain DoD Top Secret clearance.
HDL, RTL, System Verilog, Universal Verification Methodology (UVM), Xilinx ISE, Vivado, Mentor Graphics ModelSim, QuestaSim, Synplify, Electronic Design Automation (EDA) Tools, Signal Generators, Logic Analyzers, Digital Oscilloscopes, Embedded FPGA Debugging tools