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FPGA Verification Engineer Level 3/4 - Linthicum
Linthicum, Maryland, United States
$120k-$179k/yr OnsiteFull Time
3+ YOEU.S. citizen required. FPGA verification experience with VUnit, HDL (SystemVerilog/Verilog/VHDL), testbench and coverage-driven verification, RTL debug, test plan development; ability to obtain DoD Secret/Top-Secret clearance.
VUnit, SystemVerilog, Verilog, VHDL, Synopsys, Mentor Graphics, SystemVerilog Assertions (SVA), Bash, Perl, Python, Tcl, Makefile, Xilinx, MicroChip, Kintex, Zynq ultrascale+, RTG4
2mo
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FPGA Engineer (VA, Reston )
Reston, Virginia, United States
OnsiteFull Time
EndoSec: Security software and cryptographic hardware for government and defense.
Design, develop, test, and maintain FPGA IP cores and FPGA-based systems for hardware security; RTL/C/C++, Python, VHDL/Verilog; simulation, verification, system integration; verification tools and toolchains.
RTL, C/C++, Python, VHDL, Verilog, Tcl, Vivado, GHDL, Questa, Quartus Prime, Xilinx, Versal, Agilex, AXI, ACE, Avalon, IP core, cocotb, pyuvm
1mo
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Digital Design Engineer - Level 5 - Linthicum
Linthicum, Maryland, United States
$186k-$279k/yr OnsiteFull Time
7+ YOEDegree in EE/CE/CS (Bachelor’s+12yr or Master’s+10yr or PhD+7yr), FPGA/ASIC/HDL (Verilog, VHDL) experience, FPGA IDEs (Xilinx, Microsemi), test/verification and RTL debug, mentoring skills, U.S. citizenship and ability to obtain Top Secret clearance.
Xilinx, Microsemi, HDL, Verilog, VHDL, RTL
1mo
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Senior FPGA Engineer
Fairfax, Virginia, United States
$76k-$141k/yr OnsiteFull Time
4+ YOEBachelor's in EE/CE (or MS) and 6+ years (4+ with MS) experience in FPGA RTL design, timing closure, simulation/verification, Vivado/VHDL/SystemVerilog experience, lab bring‑up, and high‑speed interface integration.
Xilinx, Zynq Ultrascale+ MPSoC, Zynq Ultrascale+ RFSoC, Versal ACAP, Versal AI Engines, Vivado Design Suite, Vivado IP Integrator, Vivado HW Debugger, Chipscope, SmartDebug, Libero, Git, Modelsim, Questasim, Aldec, UVVM, UVM, OVM, VHDL, SystemVerilog, MATLAB, Simulink, Linux, C, C++
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Senior ASIC Digital Design Engineer
Annapolis Junction or Boise or Salt Lake City or Bloomington or United States
$142k-$150k/yr RemoteFull Time
5+ YOEBachelor's in ECE or related and 5+ years experience (or Master's+3); US citizenship and ability to obtain DoD Secret clearance; strong RTL/ASIC design and verification experience.
JIRA, Microsoft Office