42 rtl jobs at 11 companies in Washington
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Sr. RTL Design Engineer (Silicon Engineering)
Austin or Irvine or Redmond or Sunnyvale
$170k-$235k/yr OnsiteFull Time
5+ YOEBachelor’s in electrical/computer engineering or computer science; 5+ years of RTL implementation experience.
Verilog, SystemVerilog, Python, EDA tools, HDL simulators, HDL Lint
3w
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Principal PCIe Subsystem RTL lead
San Jose or Santa Clara or Austin or Seattle or Boston
HybridFull Time
10+ YOE10+ years digital IC design experience with 4+ years PCIe subsystem design/integration, strong SystemVerilog RTL skills, experience integrating PCIe controller/SerDes PHY, multi-clock-domain design, and ability to lead architectural work.
SystemVerilog, UVM, PCIe, CXL, SerDes
3w
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Hardware Engineer – VHDL RTL Digital Logic
Pullman, Washington, United States
$98k-$144k/yr OnsiteFull Time
Experience designing VHDL RTL digital logic for FPGAs, writing testbenches and verification, system specification and documentation, Ethernet and precise timing knowledge (PTP/IRIG-B), and project leadership.
VHDL, FPGA, Ethernet (IEEE 802.3), PTP (IEEE 1588), IRIG-B
2mo
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Senior Avionics FPGA Design & Verification Engineer - TeraWave
Seattle or Los Angeles or Denver
$157k-$220k/yr OnsiteFull Time
Blue Origin: Develops reusable rockets and systems for human spaceflight.
7+ YOE7+ years in digital design/SoC architecture; SystemVerilog/Verilog RTL; FPGA/SoC integration; timing and bus protocols; RTL simulation and debugging; hardware design verification.
SystemVerilog, Verilog, QuestaSim, FPGA, SoC, RTL, AXI, AHB
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Senior DFT Engineer
Seattle, Washington, United States
$170k-$250k/yr OnsiteFull Time
7+ YOEB.S./M.S. in EE or related, 7+ years DFT experience for complex SoCs, RTL DFT insertion, ATPG and pattern generation, MBIST/LBIST, scan architectures, low-power DFT, mixed-signal test methods, and strong RTL/gate/silicon debugging.
ATPG, MBIST, LBIST, RTL, IEEE 1149.x (JTAG)
3w
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Distinguished Engineer - Memory Architecture
Santa Clara or Austin or Redmond
$320k-$489k/yr OnsiteFull Time
18+ YOE18+ years industry/academic experience, advanced degree or equivalent experience in EE/CE/CS, expertise in memory architecture, RTL and ML-aware modeling, leadership and IP generation.
RTL, DRAM, SRAM, ML
3mo
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FPGA Engineer (WA, Seattle)
Seattle, Washington, United States
OnsiteFull Time
EndoSec: Security software and cryptographic hardware for government and defense.
Designing and maintaining FPGA IP cores and FPGA-based systems for hardware security; RTL/C/C++, Python, VHDL/Verilog, Vivado; surveillance clearance eligibility; travel up to 10%.
RTL, C/C++, Python, VHDL, Verilog, Tcl, Vivado, GHDL, Questa, Quartus Prime, Zynq, Agilex, AXI, ACE, Avalon, cocotb, pyuvm
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ASIC Engineering Technical Leader - CDC
San Jose or Austin or Seattle
$184k-$264k/yr HybridFull Time
8+ YOEExpertise in RTL development, CDC/RDC methodology, and static glitch analysis; 6–8+ years related experience (varies by degree); experience maintaining CDC/RDC flows and signing off constraints and waivers.
RTL, SDC, VCS, SystemVerilog Assertions (SVA)
1w
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Senior Physical Design Engineer
Hillsboro or Redmond or Mountain View or Raleigh or Austin
$120k-$235k/yr HybridFull Time
5+ YOEExperience in SOC physical design, low-power methodology, RTL-to-GDS implementation, signoff (timing, physical verification, EMIR, formal equivalence), and collaboration across CAD, RTL, architecture, and power teams.
PrimePower
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FPGA Engineer
El Segundo or Los Angeles or Washington or San Francisco or Seattle or London
$160k-$225k/yr OnsiteFull Time
5+ YOEBachelor's in a relevant field, 5+ years FPGA RTL design experience, Verilog/SystemVerilog, AXI protocols, Vivado and SoC FPGA experience, Bash/Python scripting, U.S. Person required.
Verilog, SystemVerilog, AXI4, AXI4-Lite, AXI4-Stream, Vivado Design Suite, Zynq, Ultrascale, Ultrascale+, Versal, TCP, UDP, IP, I2C, JTAG, UART, SPI, CAN, Bash, Python, Simulink, MATLAB, C, C++, SystemC, Chisel, VHDL, git, Bitbucket CI, Jenkins
3w
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Distinguished Engineer - Memory Architecture
Santa Clara or Austin or Redmond
$320k-$489k/yr OnsiteFull Time
18+ YOE18+ years of industry or academic experience in memory architecture, experience defining DRAM/SRAM interfaces, ML- and workload-aware modeling, RTL/microarchitecture expertise, and strong mentoring and leadership impact.
1w
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Senior ASIC Design Engineer
Vancouver, Washington, United States
$116k-$182k/yr OnsiteFull Time
8+ YOEBS/MS in electrical engineering with 8+ years ASIC/SoC design experience; RTL-to-silicon expertise, Synopsys/Cadence tool experience, Verilog/SV and scripting languages, strong communication and problem-solving skills.
Synopsys, Cadence, Verilog, SV, Python, Perl, C, C++, subversion, git, GitHub, AI Copilot
1w
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Senior ASIC Design Engineer
Vancouver, Washington, United States
$116k-$182k/yr OnsiteFull Time
8+ YOEBS/MS in electrical engineering,8+ years ASIC/SoC design experience,RTL-to-silicon expertise,experience with Synopsys and Cadence tools,proficiency in Verilog,SV,Python,Perl,C/C++,and code management (git,subversion).
Synopsys, Cadence, Verilog, SV, Python, Perl, C, C++, subversion, git, GitHub, AI Copilot
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Senior ASIC Design Engineer
Vancouver, Washington, United States
$116k-$182k/yr OnsiteFull Time
8+ YOEBS/MS in electrical engineering with VLSI focus,8+ years ASIC/SoC design experience,RTL-to-silicon expertise,knowledge of Synopsys and Cadence flows,proficiency in Verilog/SV,Python,Perl,C/C++,and code management (git,subversion).
Synopsys, Cadence, Verilog, SV, Python, Perl, C, C++, Subversion, git, GitHub, FPGA, AI Copilot (LLM-based tools)
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Member of Technical Staff - Low Level & Kernels Capabilities
San Francisco or Toronto or Seattle
$200k-$350k/yr OnsiteFull Time
Experienced low-level systems engineer fluent in C/C++/CUDA and Python, kernel and kernel-optimization experience, hardware-aware coding, familiarity with LLMs, and ability to design robust, ungameable RL environments.
C, C++, CUDA, Python, assembly, cuBLAS, FFTW, OpenSSL, FPGA, RISC-V, SIMD, AVX, TPU, RTL, HDL, HLS, MLIR, LLVM, Mojo, Triton, gem5, Lean, Coq, SMT
2d
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Senior Research Scientist, Superconducting Digital Electronics, Quantum AI
Goleta or Cambridge or Mountain View or Seattle or San Francisco or Washington
$174k-$252k/yr OnsiteFull Time
Master's in EE/Physics or equivalent, experience with superconducting logic and tape-out, published research, B.S. preferred PhD, experience in full digital design flow and low-temperature measurements preferred.
RTL, computer-aided design tools
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