261 soc jobs at 75 companies in Burnet, TX
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SoC Architect
San Diego or Austin or Chandler
$309k-$418k/yr HybridFull Time
10+ YOEArchitect scalable SoCs across market segments; deep expertise in compute, power, interconnect, caching, memory, packaging, and performance/power modeling; Bachelor's or Master's in EE/CE and 10 years senior semiconductor experience.
2mo
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SoC Design Engineer
Austin, Texas, United States
$122k-$232k/yr HybridFull Time
3+ YOEBachelor's in Electrical/Computer Engineering; 3+ years in microarchitecture/RTL design; clock domain crossing, low-power design; RTL tools, SoC integration.
RTL design, SoC integration tools, NoC architectures, Low-power design, Power-area-timing optimization
5d
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Datacenter Compute SoC Architect
San Jose or San Diego or Portland or Austin
$211k-$356k/yr OnsiteFull Time
10+ YOE10+ years SoC/compute architecture experience, 3+ years in datacenter/server SoCs; Bachelor’s degree in EE/CE/CS; expertise in CPU/memory/Interconnect, PCIe/CXL, and performance modeling.
C++, SystemC, UCIe, PCIe, CXL, ARM AMBA CHI, AXI
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SOC Platform Architect
San Diego or Austin
$212k-$318k/yr OnsiteFull Time
6+ YOEBachelor's in EE/CS (Master's/PhD highly desired) with relevant systems engineering experience (6+ years minimum depending on degree); deep SoC/IP or micro-architecture experience; strong modeling and programming skills (C++, Python).
C++, Python, Android, Linux, Windows, Zephyr, FreeRTOS
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SoC Security Architect
Santa Clara or Austin or Boston
$203k-$348k/yr OnsiteFull Time
Experienced systems architect for SoC security design, threat modeling, vulnerability assessment, cryptography, secure boot/TEE, standards participation, cross-functional leadership, and strong technical writing. BS/MS in relevant engineering/CS field preferred.
Linux, Windows
1w
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ASIC SoC Verification Engineer
Austin, Texas, United States
OnsiteFull Time
Experience in SoC/IP/Subsystem verification, SystemC/TLM and RTL verification, hardware emulation familiarity, strong problem-solving and communication; BS required (MS preferred).
SystemC, TLM, RTL, hardware emulation
2w
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Sr. Staff SoC RTL Engineer
Austin, Texas, United States
OnsiteFull Time
8+ YOEBachelors in EE/CE (or higher),8+ years ASIC/SoC RTL design,strong Verilog/SystemVerilog skills,ARM/AMBA experience,front-end ASIC flow knowledge,experience with tapeout/silicon bring-up,and US work authorization.
Verilog, SystemVerilog, ARM, AMBA, AHB, APB, AXI, LINT, CDC, RDC, UPF, FPGA
2mo
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SoC QoS/Fabric Performance Engineer, Platform Architecture
Austin, Texas, United States
OnsiteFull Time
Experience with SoC architecture, on-chip interconnects and memory Quality-of-Service; working with hardware and software engineering teams to define platform architecture.
2w
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Staff Mixed-Signal SOC Engineer – Infrastructure Power
Austin, Texas, United States
HybridFull Time
7+ YOEMSEE or equivalent, 7+ years mixed-signal SoC experience with tapeout-to-production history; deep expertise in analog, digital, verification or system architecture; automated test and silicon validation experience; mentoring ability.
2mo
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SoC Architect, Memory Subsystem
San Jose or Austin
$151k-$252k/yr OnsiteFull Time
6+ YOE6+ years in computer engineering/memory subsystems; strong knowledge of memory hierarchies, interfaces (DDR/LPDDR/HBM), controllers, caches; experience with PPA optimization; collaboration with software/hardware teams.
DDR memory interfaces, LPDDR, HBM, Memory controllers, Cache subsystems, Cache coherence protocols, Bus protocols (CHI, ACE, AXI), Android ecosystem, Arm architecture, Analysis tools
2d
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Custom SOC IP Verification Engineer
Santa Clara or Austin
$136k-$265k/yr OnsiteFull Time
5+ YOEB.S./M.S. in CE/EE or equivalent,5+ years ASIC verification experience with cache coherency and memory subsystems,SystemVerilog/UVM expertise,AMBA protocols (AXI/ACE/CHI),scripting (Python,Perl,TCL),C/C++ proficiency.
System Verilog, UVM, C++, C, Python, Perl, TCL, SVA, Palladium, Veloce
4w
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Custom SOC IP Verification Engineer
Santa Clara or Austin
$168k-$311k/yr OnsiteFull Time
6+ YOE6+ years ASIC verification experience with fabric/interconnect/NoC, strong SystemVerilog and UVM skills, knowledge of interconnect protocols (AMBA AXI, CHI), scripting (Python, Perl, TCL), and degree in computer/electrical engineering or equivalent experience.
SystemVerilog, UVM, AMBA AXI, CHI, Python, Perl, TCL, Palladium, Veloce, SVA
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Sr. SOC/ASIC Physical Design Engineer (Silicon Engineering)
Irvine or Austin or Sunnyvale
$160k-$220k/yr OnsiteFull Time
5+ YOEBachelor’s degree in electrical engineering, computer engineering or computer science; 5+ years ASIC/physical design experience; strong EDA tool knowledge; scripting skills; ability to work extended hours.
EDA tools, Python, Csh/Bash/Shell, Perl, TCL, Makefile
1w
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ASIC SoC Verification Engineer (788438)
Austin, Texas, United States
HybridFull Time
Experience in SoC/IP/SubSystem verification, SystemC/TLM and RTL environments, hardware emulation, knowledge of high-speed interfaces, strong problem-solving and communication;BS required, MS preferred.
SystemC/TLM, RTL, hardware emulation
2d
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Physical Design - SOC Top Lead
San Jose or Pittsburgh or Austin
$200k-$250k/yr OnsiteFull Time
8+ YOEEnd-to-end SOC top ownership including full-chip integration, timing closure, power/PDN analysis, physical verification, SI, clock/reset, DFT, package co-design, and tapeout readiness; advanced degree in EE and extensive PD experience.
Innovus, ICC2, Tempus, PrimeTime, RedHawk, Calibre, Voltus, TCL, shell, python
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SOC Top Level Physical Design Engineer, Annapurna Labs
Cupertino or Austin
$159k-$248k/yr OnsiteFull Time
10+ YOEBS + 10 years or MS + 7 years in EE/CS; 5+ years physical verification; experience with backend physical design flows and industry-standard tools.
Calibre, IC Validator, PVS, Innovus, FC
1mo
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Staff Digital Design Engineer – SOC Low Power, Clocking & Integration
Austin, Texas, United States
$143k-$266k/yr HybridFull Time
10+ YOEBS/MS in Electrical Engineering, 10+ years digital CMOS IC design experience, expertise in Verilog/System Verilog, UPF/CPF, AXI/AHB/APB, RTL design, synthesis, timing, power analysis, simulation, scripting (Python/Perl/Tcl), and leading small teams.
Verilog, System Verilog, UPF, CPF, AXI, AHB, APB, RISC-V, C, Python, Perl, Tcl, Perforce, Git, Methodics
1mo
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Staff Digital Design Engineer – SOC Low Power, Clocking & Integration
Austin, Texas, United States
$143k-$266k/yr HybridFull Time
10+ YOEBS/MS in EE, 10+ years digital CMOS IC design experience, Verilog/System Verilog expertise, low-power (UPF/CPF) and clocking/CDC/RDC knowledge, AXI/AHB/APB experience, scripting (Python/Perl/Tcl), and leadership of small design teams.
Verilog, System Verilog, UPF, CPF, AXI, AHB, APB, C, Python, Perl, Tcl, Perforce, Git, Methodics
1w
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ASIC Engineer, Design
Sunnyvale or Austin
$146k-$209k/yr OnsiteFull Time
6+ YOEBachelor's degree or equivalent,6+ years hardware design experience for production silicon,expertise in microarchitecture,RTL and SoC integration,strong communication and collaboration skills.
RTL, Synthesis, Timing Closure, Formal Verification Methodology, SoC, EMR
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Principal System Debug Engineer
Austin or Milpitas
OnsiteFull Time
Senior-level experience in system validation and debug for server/rack platforms, strong knowledge of Arm or x86, PCIe and CXL, OS/firmware/device driver/BIOS interactions, SoC and memory subsystems, and ability to lead cross-functional debug efforts.
PCIe, CXL, Arm, x86, Operating Systems, Device Drivers, BIOS, SoC, RAS