36 soc design jobs at 19 companies in Los Angeles, CA
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Sr. SOC/ASIC Physical Design Engineer (Silicon Engineering)
Irvine or Austin or Sunnyvale
$160k-$220k/yr OnsiteFull Time
5+ YOEBachelor’s degree in electrical engineering, computer engineering or computer science; 5+ years ASIC/physical design experience; strong EDA tool knowledge; scripting skills; ability to work extended hours.
EDA tools, Python, Csh/Bash/Shell, Perl, TCL, Makefile
3mo
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Senior Avionics FPGA Design & Verification Engineer - TeraWave
Seattle or Los Angeles or Denver
$157k-$220k/yr OnsiteFull Time
Blue Origin: Develops reusable rockets and systems for human spaceflight.
7+ YOE7+ years in digital design/SoC architecture; SystemVerilog/Verilog RTL; FPGA/SoC integration; timing and bus protocols; RTL simulation and debugging; hardware design verification.
SystemVerilog, Verilog, QuestaSim, FPGA, SoC, RTL, AXI, AHB
3mo
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FPGA Design Engineer
Irvine, California, United States
$100k-$140k/yr OnsiteFull Time
2+ YOEBS in EE or CS with 2+ years FPGA design; Xilinx FPGAs, SoCs, Vivado; TCL or Python; U.S. Person; background check and drug test.
Xilinx FPGAs, Vivado IDE, Tcl, Python, MATLAB, FPGA Design
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Principal Electronics Design Engineer
Garden Grove, California, United States
$140k-$190k/yr OnsiteFull Time
10+ YOEBSEE and 10+ years electronic systems design experience, FPGA and embedded microprocessor design, GNSS/M-Code/SAASM, Ethernet/PTP, schematic capture, team leadership, ability to obtain secret clearance and U.S. citizenship.
FPGA, PWB, GNSS, M-Code, SAASM, Ethernet, Precision Time Protocol (PTP), SoC, SoM, ASIC
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RFIC - PLL Design Engineer
Irvine, California, United States
OnsiteFull Time
Design and validate RFIC phase-locked loops (PLLs) and radio transceivers for wireless SoCs; collaborate across RF/analog, systems, VLSI, verification, test, and firmware/software teams.
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Digital Design Principal Engineer/Manager
Irvine, California, United States
$190k-$225k/yr OnsiteFull Time
20+ YOE20+ years FPGA/SoC development with leadership experience; MS in Electrical Engineering; deep Verilog/SystemVerilog expertise; FPGA/ASIC implementation and packet processing experience; scripting in C/C++, Perl, Tcl, Python.
Verilog, SystemVerilog, AMD (Xilinx Vivado), C, C++, Perl, Tcl, Python, Claude Code, Copilot
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Principal ASIC Design Verification Engineer
United States or Los Angeles
$190k-$285k/yr OnsiteFull Time
10+ YOEB.S. or M.S. in EE/CE or related, 10+ years ASIC/SoC verification, strong SystemVerilog/UVM and SVA skills, experience with VCS/Xcelium/Questa and Verdi/SimVision, scripting (Python/Perl/TCL), Git, CI/CD, C/C++, and ITAR U.S. person eligibility.
SystemVerilog, UVM, SystemVerilog Assertions (SVA), VCS, Xcelium, Questa, Verdi, SimVision, Python, Perl, TCL, Git, C, C++, CI/CD
2w
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Principal Design Validation & Test (DVT) Engineer
Irvine, California, United States
OnsiteFull Time
8+ YOE8+ years post-silicon validation/DVT experience with complex ASICs/SoCs; Bachelor's in EE/CE/CS or related; Python skills; lab equipment and high-speed protocol expertise; strong debug and communication skills.
JTAG, Python, oscilloscopes, BERTs, protocol analyzers, network analyzers, logic analyzers, Ethernet traffic generators, power measurement equipment, PCIe, Ethernet, SerDes, CXL, SPI, I²C, MDIO, RTL
1w
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Principal Engineer-Communication Systems
Irvine or San Diego
$75k-$232k/yr OnsiteFull Time
8+ YOEMaster's or PhD in Electrical Engineering, 8+ years in wireless PHY systems design, signal processing and communication theory, and experience with MATLAB, C/C++, fixed-point simulation, modem design, and IC testing.
MATLAB, C, C++, Wi-Fi, Bluetooth, SoC
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Principal Digital Engineer
Woodland Hills, California, United States
$125k-$188k/yr OnsiteFull Time
5+ YOEU.S. citizen with active Secret clearance; extensive experience in high-speed digital design and verification, FPGA/SoC/ASIC implementation (VHDL/Verilog), hardware requirements and verification processes.
VHDL, Verilog, System Verilog, UVM, MATLAB, Simulink, Hardware-In-Loop, FPGA, SoC, ASIC, DO-254
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Payload Software Engineer
Irvine, California, United States
$155k-$175k/yr OnsiteFull Time
6+ YOE6+ years in embedded software using C, C++, and Python; experience with SoC/microcontroller design, Embedded Linux/Yocto, ICD development, communication protocols, and full software lifecycle from requirements to test.
C, C++, Python, Embedded Linux, Yocto, FPGA, SoC, Microcontroller
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Digital Hardware Engineering Lead
Costa Mesa, California, United States
$170k-$255k/yr OnsiteFull Time
7+ YOEBachelors in Electrical Engineering, 7+ years designing and troubleshooting complex board designs, experience leading digital design teams, proficiency in VHDL/Verilog and Altium Designer, FPGA/SoC/SoM and high-speed interface experience, eligible for Top Secret clearance.
VHDL, Verilog, Altium Designer
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Senior Hardware Engineer, Digital
Long Beach, California, United States
$148k-$222k/yr OnsiteFull Time
5+ YOEBachelor's in EE/CE, 5+ years designing electronics for harsh, mission-critical environments; expertise in high-speed interfaces, memory and SoC/microcontroller design; experience with Altium, board bring-up, validation, and cross-functional integration.
eCAD, Altium, SPI, PCIe, Ethernet
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FPGA Engineer
El Segundo or Los Angeles or Washington or San Francisco or Seattle or London
$160k-$225k/yr OnsiteFull Time
5+ YOEBachelor's in a relevant field, 5+ years FPGA RTL design experience, Verilog/SystemVerilog, AXI protocols, Vivado and SoC FPGA experience, Bash/Python scripting, U.S. Person required.
Verilog, SystemVerilog, AXI4, AXI4-Lite, AXI4-Stream, Vivado Design Suite, Zynq, Ultrascale, Ultrascale+, Versal, TCP, UDP, IP, I2C, JTAG, UART, SPI, CAN, Bash, Python, Simulink, MATLAB, C, C++, SystemC, Chisel, VHDL, git, Bitbucket CI, Jenkins
2w
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Hardware Engineer
Colorado Springs or Irvine or Longmont or Fremont or Rochester or San Jose
$91k-$113k/yr OnsiteFull Time
Early-career candidates pursuing or recently completing an engineering degree; familiarity with hardware, firmware, ASIC/SoC, or systems; programming and design experience through coursework or projects; strong analytical and communication skills.
Verilog/SystemVerilog, RTL, FPGA, C, C++, Assembly, Python, Java, Go, SQL, JavaScript, Git, Linux, IDE, CAD, Microsoft Office, RTOS
2d
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Senior Firmware Engineer
Santa Clarita, California, United States
$124k-$135k/yr OnsiteFull Time
6+ YOEBachelor's degree in electrical or equivalent engineering, 6+ years of C/C++ embedded firmware experience, ARM Cortex-M and BLE SoC experience, regulated design controls, and strong debugging and documentation skills.
C, C++, ARM Cortex-M, Bluetooth Low Energy, Ceedling, Unity, FreeRTOS, Micrium, RTOS
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Manager Digital Engineering 2
Los Angeles, California, United States
$161k-$242k/yr OnsiteFull Time
6+ YOEU.S. citizen able to obtain security clearance; STEM bachelor's + 8 years or master's + 6 years; experience leading technical teams in digital design (FPGA/SoC/ASIC); PLM and cost estimating experience; strong communication skills.
PLM, Siemens Teamcenter Enterprise, Teamcenter Unified Architecture (UA), Tc AW – Active Workspace, MATLAB, Simulink, System Verilog, UVM, Hardware-In-Loop
13h
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Sr. Manager - Static Timing Analysis, Annapurna Labs, Cloud Scale Machine Learning
Cupertino or Los Angeles County
$240k-$324k/yr OnsiteFull Time
3+ YOEBachelor's, master's, or doctoral degree in EE/CS; 7+ years ASIC and communications experience; 3+ years static timing analysis and constraint development; expertise with EDA tools, physical design, and automation.
ASIC, EDA, PrimeTime, Tempus, PT-DMSA, Tempus-ECO, Tweaker, STAR-RC, Quantus, SPICE, SPECTRE, UVM, C, SystemC, MATLAB, Python, Embedded C, C++, Agile, TDD, BDD, CI, Git, CI/CD, SPI, I2C, I3C, UART, OFDMA, TDMA, CDMA, WiMAX, 802.11ad, DVB-S2, DVB-C, SoCs, FPGAs, NVIC, DFT
2w
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Senior Electrical Engineer, Avionics
Los Angeles, California, United States
$160k-$200k/yr HybridFull Time
6+ YOE6+ years electrical engineering experience with PCB design, circuit simulation, wire harnessing, signal integrity, and prototype debugging; experience with Altium and LTSpice; strong DC power and high-speed interface knowledge.
Altium, LTSpice, HyperLynx, SIwave, Oscilloscope, Logic analyzer, Multimeter, Spectrum analyzer, FPGA, SoC
1mo
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Principal Electrical Engineer
Denver or Louisville or Santa Monica
$200k-$250k/yr OnsiteFull Time
12+ YOE5+ MgmtBachelor's in electrical engineering, 12+ years developing complex electrical systems (5+ years leading architecture), experience with MIL-STD design, lab test equipment, and ability to obtain DoD Secret clearance; strong leadership and communication.
Altium, FPGAs, SoCs, DDR3, DDR4, PCIe 3.0, PCIe 4.0, DisplayPort, USB 3.0, Ethernet, MIL-STD-461, MIL-STD-810, MIL-STD-1553, ARINC 429, CAN, oscilloscopes, power supplies, spectrum analyzers, ISO/IEEE 15288
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