2mo
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SoC Design Engineer
Austin, Texas, United States
$122k-$232k/yr HybridFull Time
3+ YOEBachelor's in Electrical/Computer Engineering; 3+ years in microarchitecture/RTL design; clock domain crossing, low-power design; RTL tools, SoC integration.
RTL design, SoC integration tools, NoC architectures, Low-power design, Power-area-timing optimization
3mo
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SoC Design Engineer
Santa Clara, California, United States
$157k-$160k/yr OnsiteFull Time
Master’s in Electrical or Computer Engineering; ASIC/SoC design experience; RTL/verification; EDA tools; programming (Python/C++/Perl).
Verilog, SystemVerilog, PrimeTime, Cadence Virtuoso, Design Compiler, Simvision, Python, C++, Perl, SVA, HLS, EDA Tools
1mo
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Senior SOC Design Engineer
Santa Clara, California, United States
$136k-$265k/yr HybridFull Time
3+ YOEBS/MS in Computer or Electrical Engineering (or equivalent), 3+ years chip design experience focused on SoC integration and automation; expertise in RTL, SOC integration, design automation; scripting with Perl or Python; strong analytical and communication skills.
Perl, Python, RTL, EDA tools
3mo
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Debug SoC Design Engineer
Irvine or San Diego or Sunnyvale
OnsiteFull Time
Bachelor's degree required; knowledge of digital design, SoC architecture, HDL Verilog, EDA tools, microprocessor debug (CoreSight), AXI/AHB, UPF, low-power design, and strong debugging and collaboration.
Verilog, AXI, AHB, UPF, EDA tools
1mo
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SoC Design Engineer
United States
$150k-$175k/yr RemoteFull Time
5+ YOE5+ years semiconductor engineering with leadership across analog, digital (RTL), mixed-signal, and physical implementation; proven SoC/ASIC tape-out and silicon bring-up experience; B.S. in ECE or equivalent; strong operational and communication skills.
RTL, DFT, CAD, UCIe
2mo
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SOC Silicon Design Engineer
Austin or Boxborough
HybridFull Time
Design and develop custom silicon for CG SoC; collaborate across teams; strong analytical and communication skills.
Scripting (Perl, TCL, Python), EDA tools, VLSI design flow, CMOS technology
3d
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Principal Engineer, SOC Design
Folsom, California, United States
$199k-$319k/yr OnsiteFull Time
15+ YOEExtensive SoC architecture and RTL development experience with modern DRAM technologies, verification/debugging skills, FPGA prototyping or silicon bring-up experience, and strong technical leadership.
SystemVerilog, Verilog, FPGA
3d
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Senior SoC/RTL Design Engineer
San Diego, California, United States
$129k-$173k/yr OnsiteFull Time
Design, implement, and verify digital architecture and Verilog RTL for complex ASIC/SoC, perform board design and circuit debug, and collaborate with cross-functional teams.
Verilog
1mo
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HBM SoC Physical Design Engineer
Richardson, Texas, United States
OnsiteFull Time
10+ YOEImplement SoC physical designs from netlist to GDSII; proficiency with industry EDA tools, STA/SDC, power-intent (UPF/CPF), physical verification, and timing/power signoff.
Cadence Innovus, Cadence Tempus, Synopsys ICC2, Synopsys PrimeTime, Siemens Calibre, GDSII, SDC, UPF, CPF
3mo
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Senior Director of SoC Design
San Diego, California, United States
$227k-$336k/yr OnsiteFull Time
15+ YOE5+ MgmtLead a multi-disciplinary SoC design organization; 15+ years RTL/verification; 5+ years design leadership; BS in EE/CE/CS; ability to recruit and mentor.
1mo
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HBM SoC Physical Design Engineer
Richardson, Texas, United States
OnsiteFull Time
10+ YOEHands-on SoC physical design from netlist to GDSII on advanced nodes; proficiency with industry EDA tools, STA/SDC, power intent (UPF/CPF), physical verification, and strong timing/power optimization skills.
Cadence Innovus, Cadence Tempus, Synopsys ICC2, Synopsys PrimeTime, Siemens Calibre, GDSII, SDC, UPF, CPF
2w
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Lead SoC Design Engineer
Los Altos, California, United States
OnsiteFull Time
Anodize: Developing next-generation personal computing hardware and consumer electronics.
10+ YOE10+ years developing complex ASICs; Bachelor's in EE/CE (or equivalent); deep knowledge of AMBA protocols, Verilog/SystemVerilog/SVA, SDC timing constraints, multi-power-domain design and UPF; experience with ASIC CAD flows.
AMBA AXI, AXI-S, APB, Verilog, SystemVerilog, SystemVerilog Assertions (SVA), SDC, STA, Lint, CDC, RDC, LEC, UPF, UCIe, DDR, Arm
2w
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Senior SoC Digital Design Engineer, Multimedia Lab
San Jose, California, United States
$213k-$450k/yr OnsiteFull Time
3+ YOEBachelor's in EE/CS or related, 3+ years front-end digital/SoC design, mastery of Verilog/SystemVerilog, experience with front-end EDA tools, scripting (Python/Perl/Tcl/Makefile), and low-power design techniques.
Verilog, SystemVerilog, Spyglass, Design Compiler, PrimeTime, Python, Perl, Tcl, Makefile, UPF, SDC, STA
1mo
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SoC RTL Design Engineer
San Jose or Bangalore
HybridFull Time
8+ YOEBS/MS in Electrical or Computer Engineering; 8+ years in digital IC design with chip infrastructure ownership (clocking, power management, reset/DFT) at block-lead or subsystem level; strong SystemVerilog and infrastructure RTL skills; experience with embedded microcontroller integration and security features.
SystemVerilog, RTL Design, Power Management, Clock Gating, Reset, DFT, BIST, Interrupt Controller, UART, JTAG, PCIe, UCIe
5d
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TPU SoC Design Engineer, Google Cloud
Sunnyvale, California, United States
$116k-$166k/yr OnsiteFull Time
2+ YOEBachelor's degree or equivalent,2+ years ASIC RTL design with SystemVerilog/Verilog,experience with EDA tools,knowledge of digital design,EMR not required,excellent communication and critical thinking.
SystemVerilog, Verilog, Python, Tcl, Perl, Verdi, VCS, AXI, CDC, UPF, RDC, LEC
3mo
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Design Verification Engineer - SoC
San Jose, California, United States
$150k-$275k/yr OnsiteFull Time
Design verification for ASIC/SoC; SystemVerilog and Python; performance modeling; test benches and verification infrastructure.
SystemVerilog, Python
3mo
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SOC Architect
Santa Clara or Cambridge or France or Oregon or Boston
$254k-$311k/yr OnsiteFull Time
10+ YOEMS or PhD in Computer Science / Computer Architecture; 10+ years in SoC architecture; 5+ years in engineering teams; experience in SoC design flow, architecture, and performance modeling; CPU architectures, power management, platform hardware, OS, drivers, and firmware.
3mo
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SOC Architect
San Francisco, California, United States
$266k-$445k/yr OnsiteFull Time
Define architecture for custom SoCs; lead hardware/software co-design; deep AI/ML accelerator knowledge; cross-functional leadership.
RTL, ASIC, SoC design, edge AI
1mo
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SOC Manager
Washington or Maryland
$80k-$120k/yr RemoteFull Time
5+ YOE2+ MgmtManage SOC tools and a team of analysts; design and test security architectures; 5+ years experience (7 preferred); 3+ years SOC/cyber experience; US citizen able to obtain Public Trust; 2+ years leadership; risk analysis and senior briefing experience.
Splunk, ServiceNow, Palo Alto, Archer, Nessus, Microsoft Exchange Online Protection, CrowdStrike, Trellix (NX/CM/AX), Cisco ISE
1mo
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Sr. SOC/ASIC Physical Design Engineer (Silicon Engineering)
Irvine or Austin or Sunnyvale
$160k-$220k/yr OnsiteFull Time
5+ YOEBachelor’s degree in electrical engineering, computer engineering or computer science; 5+ years ASIC/physical design experience; strong EDA tool knowledge; scripting skills; ability to work extended hours.
EDA tools, Python, Csh/Bash/Shell, Perl, TCL, Makefile
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