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Principal Design Verification Engineer
Austin or Colorado or Malta
$153k-$265k/yr OnsiteFull Time
8+ YOEBachelor's in engineering, 8+ years verification experience (CPU/SoC preferred). Hands-on SystemVerilog, UVM, constrained random, Python/Perl/Shell scripting; familiarity with CPU architectures and cache/coherency concepts.
SystemVerilog, UVM, C, Assembly, Python, Perl, Shell, AXI, ACE, CHI
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Principal Design Verification Engineer
Austin or Texas or Santa Clara or Malta
$153k-$290k/yr OnsiteFull Time
8+ YOEBachelor's in engineering, 8+ years design verification (CPU/SoC) experience, hands-on SystemVerilog/UVM and constrained-random verification, scripting in Python/Perl/Shell, familiarity with CPU architectures and cache/coherency concepts.
SystemVerilog, UVM, C, Assembly, Python, Perl, Shell
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Sr Principal Verification Engineer
Austin or Texas or Malta
$171k-$296k/yr OnsiteFull Time
15+ YOEBachelor's in EE/Elec/Comp Eng, 15+ years in design verification (CPU/SoC preferred). Hands-on SystemVerilog, UVM, constrained-random, scripting (Python/Perl/Shell), familiarity with RISC-V/ARM/MIPS, cache/coherency concepts.
SystemVerilog, UVM, C, Assembly, Python, Perl, Shell, FPGA, RISC-V, ARM, MIPS, AXI, ACE, CHI
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FPGA Designer
Niskayuna, New York, United States
$120k-$180k/yr HybridFull Time
Bachelor's or Master’s in EE/CE/CS, strong synchronous digital design and embedded firmware (C/C++), FPGA development (VHDL/Verilog), timing closure and verification tools, familiarity with SoC platforms; onsite Tue–Thu (hybrid).
VHDL, Verilog, QuestaSim, Quartus, Xcelium, C, C++, Altera, Xilinx, Zynq, MATLAB/Simulink