1,608 soc engineer jobs at 538 companies in United States
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Chief SoC Engineer
United States
$200k-$250k/yr RemoteFull Time
10+ YOE10+ years semiconductor experience with SoC/ASIC design leadership, proven tape-out and silicon bring-up track record, strong analog/mixed-signal and RTL expertise, program leadership, BS in Electrical/Computer Engineering or equivalent.
2w
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Senior SoC Verification Engineer
Toronto or Europe or United States or France or Hungary
$126k-$170k/yr HybridFull Time
4+ YOEBachelor's or master's degree in computer science or electrical/computer engineering and 4+ years in sophisticated compute subsystem or SoC design or verification. Requires Verilog HDL, SoC verification, PCIe/CXL, DDRx/LPDDRx, HBM, C, and Assembly.
SystemVerilog, Verilog, Verilog HDL, PCIe, CXL, DDRx, LPDDRx, HBM, C, Assembler, UVM, OVM, Perl, Python
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Senior SOC Design Engineer
Santa Clara, California, United States
$136k-$265k/yr HybridFull Time
3+ YOEBS/MS in Computer or Electrical Engineering (or equivalent), 3+ years chip design experience focused on SoC integration and automation; expertise in RTL, SOC integration, design automation; scripting with Perl or Python; strong analytical and communication skills.
Perl, Python, RTL, EDA tools
3w
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Senior SOC Physical Design Engineer
Austin, Texas, United States
$124k-$173k/yr OnsiteFull Time
Master's degree in electrical engineering, computer engineering, computer science, or a related field; independently performs SoC physical design, verification, timing closure, and tapeout signoff activities.
LVS, DRC, SoC, PDN
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Principal Engineer, SOC Integration
San Jose, California, United States
$219k-$351k/yr OnsiteFull Time
18+ YOEBS/MS in Computer/Electrical Engineering or CS with extensive ASIC/SoC experience (18+ years MS or 20+ years BS). Hands-on ASIC tape-out, commercial IPs (UCIe, CPU, DDR, Ethernet), SoC synthesis/timing/DFT, AMBA/ARM experience.
UCIe, ARM, DDR, Ethernet, AMBA, DFT, CDC
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Senior SOC Design Engineer
Santa Clara, California, United States
$136k-$265k/yr HybridFull Time
3+ YOEBachelor's or master's in computer or electrical engineering, 3+ years of chip design experience, SOC integration and automation expertise, RTL proficiency, and Perl or Python scripting skills.
Perl, Python, RTL, EDA
4w
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SOC Engineer
Homewood, Illinois, United States
$90k-$115k/yr OnsiteFull Time
3+ YOEBachelor's or equivalent and 3+ years SOC experience, CompTIA Network+ and Security+ required; strong incident response, threat detection, and cross-functional communication skills.
Security Information and Event Monitoring (SIEM)
4w
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SOC Engineer
Homewood, Illinois, United States
$90k-$115k/yr OnsiteFull Time
3+ YOE3+ years SOC experience supporting multiple sites, Bachelor's degree or equivalent, CompTIA Network+ and Security+ required, experience with SIEM, incident response, and security tools.
SIEM
3w
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Staff SoC RTL Engineer
Burlingame, California, United States
$175k-$230k/yr HybridFull Time
5+ YOEBS, MS, or Ph.D. in electrical or computer engineering; 5+ years of SoC/ASIC front-end design and integration; SystemVerilog or Verilog; computer architecture, low-power design, subsystem, and VCS experience.
SystemVerilog, Verilog, VCS, C++, FPGA
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SOC Engineer
Kansas City or Overland Park or Sarasota or Scottsdale
OnsiteFull Time
5+ YOE5+ years in security operations/incident response; strong telemetry and SIEM experience; cloud security knowledge (AWS/Azure/GCP); scripting in Python or PowerShell; SOC automation and SOAR familiarity.
Google Chronicle, Microsoft Sentinel, Splunk, Splunk Enterprise Security, SIEM, SOAR, Python, PowerShell, AWS, Azure, GCP, Terraform, CloudFormation, Kubernetes, LLM
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SoC QoS/Fabric Performance Engineer, Platform Architecture
Cupertino, California, United States
OnsiteFull Time
Experienced SoC performance engineer to work with hardware and software teams to shape SoC architecture and develop on-chip interconnect and memory QoS features.
2w
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SoC DFT Engineer, Cloud
Sunnyvale, California, United States
$163k-$236k/yr OnsiteFull Time
5+ YOEBachelor's degree or equivalent practical experience, 5 years in SoC DFT architecture, implementation, and verification, silicon DFT debug or validation, and experience with ATE, MBIST, JTAG, or SLT.
ATE, MBIST, JTAG, System Level Test (SLT), Synopsys, Design Compiler, DFT Max, Siemens EDA, Tessent, TestKompress, IEEE 1149.1, IEEE 1687, BSDL, STIL, TPU, Scan, iJTAG, ATPG, TDRC, Logic BIST, TAP controllers
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SOC Performance Engineer
Austin, Texas, United States
$145k-$217k/yr OnsiteFull Time
Experience with computer architecture, system simulation, performance evaluation, bottleneck analysis, mathematical modeling, microarchitecture, and C/C++ programming; degree in engineering or computer science preferred.
C, C++
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SoC Design Engineer
Santa Clara, California, United States
$157k-$160k/yr OnsiteFull Time
1+ YOEMaster's in Electrical or Computer Engineering required, 1+ year digital design experience; RTL/Verilog, SystemVerilog/SVA, Python, Perl; experience with Synopsys PrimeTime, Cadence Virtuoso, Design Compiler, Integrator; FPGA prototyping, STA, DFT.
Synopsys PrimeTime, Cadence Virtuoso, Design Compiler, Integrator, SystemVerilog, SVA, Python, Perl, Verilog, FPGA
1mo
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HBM SoC Physical Design Engineer
Folsom, California, United States
$121k-$205k/yr OnsiteFull Time
3+ YOEExperience implementing SoC physical design from netlist to GDSII, STA and signoff knowledge, EDA tool proficiency, 3+ years relevant experience, and ability to mentor engineers.
Cadence Innovus, Cadence Tempus, Synopsys ICC2, Synopsys PrimeTime, Siemens Calibre, UPF, CPF, SDC
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SoC Logic Design Engineer
Austin or Santa Clara or Hillsboro
$142k-$200k/yr HybridFull Time
3+ YOEExperience in RTL/Verilog logic design, SoC integration, low-power and timing optimization, Clock Domain Crossing and NoC architectures, AMBA protocols; bachelor's or master's in EE/CE with relevant years of experience.
RTL, Verilog, AMBA, CHI, AXI, AHB, APB, Network-on-Chip (NoC), Clock Domain Crossing
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Sr. Staff SoC RTL Engineer
Austin, Texas, United States
OnsiteFull Time
8+ YOEBachelors in EE/CE (or higher),8+ years ASIC/SoC RTL design,strong Verilog/SystemVerilog skills,ARM/AMBA experience,front-end ASIC flow knowledge,experience with tapeout/silicon bring-up,and US work authorization.
Verilog, SystemVerilog, ARM, AMBA, AHB, APB, AXI, LINT, CDC, RDC, UPF, FPGA
2mo
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HBM SoC Physical Design Engineer
Richardson, Texas, United States
OnsiteFull Time
10+ YOEImplement SoC physical designs from netlist to GDSII; proficiency with industry EDA tools, STA/SDC, power-intent (UPF/CPF), physical verification, and timing/power signoff.
Cadence Innovus, Cadence Tempus, Synopsys ICC2, Synopsys PrimeTime, Siemens Calibre, GDSII, SDC, UPF, CPF
3mo
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Sr. Principal Engineer, SoC Architect
San Jose, California, United States
$250k-$304k/yr OnsiteFull Time
15+ YOE15+ years in SoC/system architecture; strong high-speed I/O and interconnect knowledge; leadership, cross-functional collaboration.
PCIe, PCIe Gen5, PCIe Gen6, CXL/UCIe, HBM, SerDes, Ethernet, USB, Memory interconnect, Interconnect
3w
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SoC Architect
North America or San Francisco or Austin or Boston
HybridFull Time
Requires ownership of specifications and implementation for at least one SoC or die, deep architecture, microarchitecture, and physical design expertise, and experience coordinating cross-functional SoC development.
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