10 soc engineer jobs at 5 companies in Cheyenne, WY
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Principal IC SoC Integration and Design Engineer
Mendota Heights or Fort Collins or Broomfield
$129k-$207k/yr OnsiteFull Time
10+ YOEBachelor's (EE/CE/CS) +12 yrs or Master's +10 yrs; expertise in Verilog/VHDL/SystemVerilog, AMBA, high-speed SERDES/DRAM interfaces, physical implementation and timing closure; strong communication and collaboration; US work authorization required.
AMBA, UART, DRAM, SERDES, Verilog, VHDL, SystemVerilog
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Lead Firmware Engineer (C++ Embedded)
Fort Collins, Colorado, United States
$115k-$180k/yr OnsiteFull Time
8+ YOE8+ years in real-time embedded firmware development using C/C++; leadership at hardware-firmware interface; experience with control systems, signal processing, microcontrollers/FPGA/SoC, and communication protocols (I2C, SPI, CAN, Ethernet, USB, UART).
C/C++, I2C, SPI, CAN, Ethernet, USB, UART, DDR3/4, Xilinx Zynq, ARM Cortex-M, FPGA, SoC, microcontroller
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Senior Electrical Engineer
Broomfield or Fort Collins
$126k-$167k/yr OnsiteFull Time
8+ YOEBachelor's in Electrical Engineering, 8+ years designing and troubleshooting complex hardware and embedded systems; experience with SERDES, DDR, Ethernet, FPGAs, SPI/I2C, signal/power integrity, Altium, Python, and lab test equipment; eligible for U.S. Secret clearance.
Altium Designer, Python, Oscilloscope, DMM, Logic analyzer, Spectrum analyzer, Current probe, SERDES, DDR, Ethernet, FPGA, SPI, I2C, PCIe, JESD204, SoC
3w
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STA Engineer
Fort Collins, Colorado, United States
$129k-$207k/yr OnsiteFull Time
10+ YOEDeep STA and timing-closure expertise for large SoC designs, strong timing analysis, familiarity with noise/cross-talk/OCV, circuit modeling, Perl/TCL scripting; MSEE and extensive industry experience.
STA, Perl, TCL, SPICE
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Physical Design Engineer, PnR
Austin or Fort Collins or Santa Clara
$100k-$500k/yr HybridFull Time
Synthesize, PNR, and STA for AI SoC partitions; use Synopsys tools; collaborate in a small PD team; knowledge of UPF/power domains and IP integration is a plus.
Synopsys Design Compiler, Fusion Compiler, IC Compiler II, Power domain tools, LEC/Formality, DRC/LVS, EM/IR, UPF, DFT (OCC/MBIST)
3w
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Digital Design RTL Engineer
Fort Collins or San Jose
$122k-$195k/yr OnsiteFull Time
8+ YOEBSEE required; 8+ years experience in SoC integration with RTL design in advanced nodes, SystemVerilog proficiency, PPA/CDC/RDC and low-power design knowledge; EMR not mentioned.
SystemVerilog
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CPU Core Physical Design Thermal Modeling Lead
Santa Clara or Austin or Fort Collins or Boxborough
$175k-$300k/yr HybridFull Time
Requires a bachelor's or master's degree in computer or electrical engineering, strong physical design and EDA experience, SoC/IP design knowledge, package modeling familiarity, and scripting and flow automation expertise.
EDA, SoC, IP
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Digital Design RTL Engineer
Fort Collins or San Jose
$122k-$195k/yr OnsiteFull Time
8+ YOEProven SystemVerilog RTL development in advanced nodes, 8+ years SoC experience, BSEE required (MSEE/PhD preferred), experience with PPA optimization, CDC/RDC, low-power design, and high-speed memory/SerDes protocols.
SystemVerilog
3w
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Digital Design RTL Engineer
Fort Collins or San Jose
OnsiteFull Time
Expert SystemVerilog RTL for advanced nodes, 8+ years experience, BSEE required (MSEE/PhD preferred), SoC integration experience, SerDes/DDR/HBM protocols, CDC/RDC, low-power and PPA optimization, timing closure and cross-team collaboration.
SystemVerilog
3mo
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Full-Chip Physical Design Verification Engineer
Austin or Fort Collins or Santa Clara
$100k-$500k/yr HybridFull Time
7+ YOE7–14 years of hands-on CPU/IP/SoC physical verification experience; strong DRC/LVS/ERC/DFM tooling skills; scripting in Python and TCL.
Calibre, ICV, Pegasus, FC, Innovus, Python, TCL