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SoC Verification Engineer – NoC / UVM
San Jose, California, United States
$146k-$250k/yr HybridFull Time
Expertise in SystemVerilog and UVM, ASIC/SoC verification, constraint-random and coverage-driven methodologies, formal verification (SVA); experience with Synopsys VCS and Cadence IES preferred; B.S. or M.S. in computer/electrical engineering.
SystemVerilog, UVM, OVM, VMM, Verilog, SystemVerilog Assertions (SVA), Synopsys VCS, Cadence IES, Cadence IEV, Jasper, Synopsys VC-Formal, Magellan
1mo
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SoC Physical Integration Engineer
San Jose, California, United States
$104k-$178k/yr HybridFull Time
Bachelor's degree in EE (Master's preferred); experience in SoC physical/electrical verification and tape-out; familiarity with physical implementation and P&R tools; simulation with SPICE/Verilog; scripting (Perl, Python, TCL, C-shell, Make); Unix/Linux.
Virtuoso, ICC2, FC, Innovus, SPICE, Verilog, RTL, Place and Route (P&R), Perl, Python, TCL, C-shell, Make, Unix/Linux, CAD
3w
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SoC Architect
San Jose, California, United States
HybridFull Time
Expertise architecting SoC and I/O subsystems (PCIe/CXL/UAL), BS/MS/PhD in electrical or computer engineering or related field, strong communication, and domain experience in embedded/data-center/automotive/aerospace.
PCIe, CXL, UAL, Confidential Compute, FPGA, AXI, x86, RISC-V, ARM
1mo
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Lead - SoC Architect
San Jose, California, United States
$235k-$402k/yr OnsiteFull Time
MS or PhD in Electrical/Computer Engineering (required). Expert in heterogeneous SoC architecture (CPUs, GPUs, AI accelerators), memory and interconnect design, system-level modeling, and technical leadership across cross-functional teams.
6d
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SoC Design Verification Engineer
San Jose, California, United States
$124k-$213k/yr HybridFull Time
Experience in SoC/CPU verification, testbench development, and verification metrics; strong coding in Verilog/System Verilog, UVM, C/C++, scripting (Perl/Python); Bachelors/Masters in computer or electrical engineering.
Verilog, System Verilog, UVM, C, C++, Perl, Python
2mo
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Product Planning Engineer-ASIC/SoC
San Jose, California, United States
$140k-$240k/yr OnsiteFull Time
Experience in product planning for next-generation AMD Adaptive and Embedded Computing products; strong collaboration across architecture, design, and product teams; ability to drive technical decisions independently.
Power estimation, Power delivery, Thermal solutions, FPGA, Adaptive SoCs, Embedded x86, ASICs, ASSPs, Product planning, Data analysis
2mo
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FPGA / VLSI Engineer
Saratoga, California, United States
$120k-$220k/yr OnsiteFull Time
Design and verify RTL/FPGA, perform FPGA prototyping, and system integration for ASIC/SoC platforms; strong SystemVerilog/Verilog; experience with UVM; VHDL is a plus.
SystemVerilog, Verilog, UVM, VHDL, FPGA, SoC
3w
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Firmware Architect (SoC / Embedded Systems)
San Jose, California, United States
$146k-$250k/yr HybridFull Time
Expertise in SoC boot and firmware architecture for ARM/x86, firmware development, functional safety (ISO 26262) knowledge, BS/MS/PhD in engineering, strong analytical and communication skills.
C, Python
3w
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RTL Design Engineer
San Jose, California, United States
HybridFull Time
Experience in RTL digital design and verification, Verilog/System Verilog, scripting (Perl/Tcl/Python), FPGA/SoC design concepts, and strong analytical and communication skills; Bachelor’s or Master’s in Computer or Electrical Engineering.
Verilog, System Verilog, Perl, Tcl, Python
2w
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FPGA Engineer: Physical AI & Robotics
San Jose or Austin
HybridFull Time
Experienced FPGA/Adaptive SoC engineer with FPGA RTL and embedded software skills, familiarity with Verilog/SystemVerilog/VHDL, C/C++, Embedded Linux/Yocto, hardware debugging, and ability to work with customers on Physical AI solutions.
AMD Vivado, Vitis, Vitis HLS, Yocto, Verilog, SystemVerilog, VHDL, C, C++, PCIe, Ethernet, DisplayPort, MIPI CSI/DSI, USB, CAN, SPI, I2C, UART, GPIO, ROS 2, Git, JTAG, oscilloscope, protocol analyzer, logic analyzer
2mo
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Senior ASIC Design Engineer – Processor Subsystem
Saratoga, California, United States
$150k-$220k/yr OnsiteFull Time
7+ YOESenior ASIC/SoC design with processor subsystem integration and RTL expertise.
SystemVerilog, VHDL, AMBA (AHB, APB, AXI), Synopsys VCS, Cadence Xcelium, Mentor Questa
2mo
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Senior EM/IR Engineer
Saratoga, California, United States
$120k-$220k/yr OnsiteFull Time
8+ YOE8+ years EM/IR analysis for complex ASICs/SoCs; power integrity; PDN design and sign-off; Verilog/SystemVerilog/UVM; scripting (Python/Tcl); experience with Cadence Voltus and Synopsys RedHawk.
Cadence Voltus, Synopsys RedHawk, Verilog, SystemVerilog, UVM, VHDL, Tcl, Python
1mo
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Senior Field Security Applications Engineer
Campbell or Austin or United States
$140k-$190k/yr FieldFull Time
5+ YOE5+ years SoC design and verification experience with Verilog/VHDL/SystemVerilog, RTL simulation/emulation tools, strong presentation skills, willingness to travel, US citizenship required.
Verilog, VHDL, SystemVerilog, RTL Simulation, Emulation, Synopsys, Cadence, Siemens, Cycuity Radix, Cycuity HW, FPGA-based Prototyping
1mo
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Principal Software Engineer, Security Solutions
Campbell, California, United States
$195k-$210k/yr HybridFull Time
8+ YOE8+ years building complex C++ commercial applications, strong algorithms/data-structures background, EDA and SoC domain experience, familiarity with Verilog/SystemVerilog/VHDL, Linux proficiency, leadership and communication skills; BS in CS/EE (MS/PhD preferred).
C++, Linux, Verilog, SystemVerilog, VHDL
1w
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Sr. Manager System Architect
San Jose or Santa Clara
$158k-$271k/yr HybridFull Time
Bachelor's in engineering required; proven experience designing wired subsystems with FPGA/SoC/ASIC, RTL/FPGA tools, Ethernet and networking expertise, system architecture, benchmarking, power/thermal optimization, project management, and AI/ML tool use.
FPGA, SoC, ASIC, RTL, FPGA tools, AI ML tools
2w
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T2021 - Information Security Engineer
Seaside, California, United States
$115k-$135k/yr HybridFull Time
3+ YOEBachelor's in computer science or related field, U.S. citizen with active Secret clearance, DoD 8570 IAT Level II cert, 3+ years IR/SOC experience, knowledge of NIST SP 800-61 and ATT&CK, familiarity with Trellix/ESS, Tanium, Microsoft Defender Endpoint, BeyondTrust, and Splunk.
Trellix/ESS, Tanium, Microsoft Defender Endpoint, BeyondTrust, Splunk
1mo
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Technical Program Manager, Pre-Silicon Development
San Jose, California, United States
$160k-$240k/yr HybridFull Time
Hands-on program leader with BS/MS in engineering (or equivalent competency), strong project management skills, silicon/SoC experience (RTL, verification, physical design), FPGA HW/SW preferred, and ability to present to executives.
RTL, FPGA
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Fellow - FPGA architecture
San Jose, California, United States
$235k-$402k/yr OnsiteFull Time
Expertise in FPGA configuration and Partial Reconfiguration, bitstream and boot flows, configuration security, ASIC/SoC design experience, and leadership in architecture definition and mentorship.
2w
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FPGA Prototyping Lead
San Jose, California, United States
$200k-$300k/yr HybridFull Time
12+ YOESenior FPGA prototyping leader with deep FPGA/SoC expertise, 12+ years experience preferred, Bachelor's or Master's in EE/CE, strong SystemVerilog/Verilog and Vivado/Vitis experience.
Synopsys HAPS, Cadence Protium, AMD/Xilinx Vivado, Vitis, SystemVerilog, Verilog
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