2 soc verification engineer jobs at 2 companies in New York City, NY

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RTL Design Engineer
New York City or Palo Alto or London
$205k-$285k/yr HybridFull Time
Normal Computing
Normal Computing: Building probabilistic AI and thermodynamic computing for semiconductor design.
Production SystemVerilog RTL experience, verification with UVM/cocotb/formal, taped-out silicon, ASIC/SoC design background, simulation and timing collaboration experience.
SystemVerilog, UVM, cocotb, formal, Chipyard, OpenTitan, CVA6, RISC-V
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Senior Engineer, Physical Design Engineering (ASIC)
Somerset County or Wilmington
$117k-$161k/yr OnsiteFull Time
Analog Devices
Analog DevicesNASDAQ: ADI: Designs and manufactures semiconductors for signal processing and power management.
5+ YOEExpertise in ASIC/SoC physical design, floorplanning, P&R, timing closure, physical verification, scripting (TCL/Python), and cross-functional collaboration; 5+ years experience preferred.
Cadence, TCL, Python