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Staff SoC Verification Engineer
San Diego, California, United States
$115k-$170k/yr OnsiteFull Time
3+ YOEBS in engineering with 3-5+ years in verification; strong SoC verification, UVM, SystemVerilog, C/C++, DPI; teamwork and problem solving.
UVM, SystemVerilog, C, C++, DPI
1mo
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Wireless SOC Verification Engineer
San Diego, California, United States
OnsiteFull Time
Experience verifying complex SoCs, building reusable UVM testbenches, developing coverage-driven and directed tests, and deploying AI tools to improve verification and tape-out readiness.
UVM
1mo
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SoC Verification Engineer – NoC / UVM
San Jose, California, United States
$146k-$250k/yr HybridFull Time
Expertise in SystemVerilog and UVM, ASIC/SoC verification, constraint-random and coverage-driven methodologies, formal verification (SVA); experience with Synopsys VCS and Cadence IES preferred; B.S. or M.S. in computer/electrical engineering.
SystemVerilog, UVM, OVM, VMM, Verilog, SystemVerilog Assertions (SVA), Synopsys VCS, Cadence IES, Cadence IEV, Jasper, Synopsys VC-Formal, Magellan
1mo
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SoC Verification Lead
Santa Clara, California, United States
$232k-$368k/yr OnsiteFull Time
15+ YOE15+ years ASIC/SoC functional verification experience; degree in EE/CE or equivalent; strong SystemVerilog/UVM and C/C++ skills; SoC-level verification and tape-out sign-off experience; leadership and risk mitigation experience.
SystemVerilog, UVM, C, C++, FPGA, EDA
1mo
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SoC Verification Lead
Santa Clara, California, United States
$232k-$368k/yr OnsiteFull Time
15+ YOE15+ years of ASIC/SoC functional verification experience; Bachelor's/Master's in EE/CE or equivalent; proficiency in SystemVerilog, UVM, C/C++; experience leading verification to tape-out and managing verification plans, schedules, and risk.
SystemVerilog, UVM, C, C++, EDA
3w
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SOC Verification and Methodology Engineer
San Diego, California, United States
$164k-$246k/yr OnsiteFull Time
6+ YOEDevelop and execute SystemVerilog/UVM verification plans for SoC designs; debug issues; collaborate with cross-functional teams. Bachelor’s (or higher) in science/engineering plus relevant ASIC verification experience required.
SystemVerilog, UVM, Perl, Python, Formal tools
1w
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Lead SoC Verification Engineer
Los Altos, California, United States
OnsiteFull Time
Anodize: Developing next-generation personal computing hardware and consumer electronics.
10+ YOE10+ years verifying complex ASICs; BS/MS in EE or CE; deep knowledge of AMBA interconnects; fluent in SystemVerilog/SystemC and UVM; UPF and multi-power-domain verification experience; proven silicon bring-up track record.
SystemVerilog, SystemC, UVM, AMBA CHI, AMBA AXI, AXI-S, APB, UPF
3d
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Senior SoC Design Verification Engineer
Folsom or Santa Clara
$164k-$269k/yr HybridFull Time
8+ YOE8+ years SoC verification experience, bachelor’s in EE/CE/CS, SystemVerilog/OVM/UVM expertise, debugging in pre-silicon, scripting with Python, strong communication and technical leadership.
System Verilog, OVM, UVM, Python
3mo
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Design Verification Engineer - SoC
San Jose, California, United States
$150k-$275k/yr OnsiteFull Time
Design verification for ASIC/SoC; SystemVerilog and Python; performance modeling; test benches and verification infrastructure.
SystemVerilog, Python
2w
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SoC Physical Verification Engineer, HBM
Richardson or Folsom
$97k-$205k/yr OnsiteFull Time
Hands-on physical verification expertise (DRC,LVS,ERC,PERC,DFM), experience with advanced-node SoC/HBM verification, foundry rule deck execution, scripting (Python/Tcl/Perl), and cross-functional collaboration for tape‑out sign‑off.
Calibre, IC Validator (ICV), Pegasus, Python, Tcl, Perl
2w
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SoC Digital Verification Engineer, Multimedia Lab
San Jose, California, United States
$156k-$317k/yr OnsiteFull Time
1+ YOEBachelor's in a related field,1+ years ASIC/SoC verification experience,mastery of SystemVerilog and UVM,proficiency with simulation/debug tools and Python/Perl/Shell scripting.
SystemVerilog, UVM, VCS, Incisive, Questa, Verdi, Python, Perl, Shell, Palladium, ZeBu, JasperGold, FPGA, ASIC
3mo
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Staff/Principal Engineer - Design Verification (SoC expert/lead)
San Jose, California, United States
$168k-$336k/yr OnsiteFull Time
10+ YOE10+ years SoC verification; SystemVerilog/UVM; PCIe/NVMe/NAND/DDR; emulation; Gen-AI tools; leadership in verification
SystemVerilog, UVM, PCIe, NVMe, NAND, DDR, emulation, Gen-AI tools
5d
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SoC Design Verification Engineer (2026 New College Graduate)
Richardson, Texas, United States
$86k-$148k/yr OnsiteFull Time
0+ YOEBachelor's in EE/CE or related, 0-2 years digital verification experience, Verilog/SystemVerilog, Python/Tcl/Perl, UNIX/EDA tools, strong analytical and communication skills.
Verilog, SystemVerilog, Python, Tcl/Tk, Perl, UNIX, EDA design tools, RISC-V, ARM, MIPS, C, C++
5d
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SoC Design Verification Engineer (2026 New College Graduate)
Richardson, Texas, United States
$86k-$148k/yr OnsiteFull Time
0+ YOEBachelor's in EE/CE,0-2 years digital verification experience, proficiency with Verilog/SystemVerilog, scripting (Python,Tcl/Tk,Perl), UNIX and EDA tools, strong analytical and communication skills.
Verilog, SystemVerilog, Python, Tcl/Tk, Perl, C, C++, UNIX, EDA design tools
2w
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Verification Engineer
San Jose, California, United States
OnsiteFull Time
3+ YOEBS/MS in ECE (or equivalent), 3+ years ASIC/SoC functional verification, strong UVM/SystemVerilog skills, testbench development, scripting in Python/Perl/TCL, and familiarity with regression/CI and hardware-assisted verification.
UVM, SystemVerilog, Python, Perl, TCL, Verilog-AMS, Palladium, Veloce, HAPS, Protium, UPF, UCIe, PCIe, CXL, Ethernet, UALink, VIP
3mo
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SoC Design Engineer
Santa Clara, California, United States
$157k-$160k/yr OnsiteFull Time
Master’s in Electrical or Computer Engineering; ASIC/SoC design experience; RTL/verification; EDA tools; programming (Python/C++/Perl).
Verilog, SystemVerilog, PrimeTime, Cadence Virtuoso, Design Compiler, Simvision, Python, C++, Perl, SVA, HLS, EDA Tools
3w
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Staff Verification Engineer
Pittsburgh, Pennsylvania, United States
$120k-$200k/yr OnsiteFull Time
5+ YOE5+ years ASIC/SoC verification experience, Bachelor’s or Master’s in electrical/computer engineering, expertise in SystemVerilog/UVM, constrained-random and assertion verification, scripting in Python/Perl/Tcl/shell, Cadence/Mentor/Synopsys tool experience, protocol knowledge (Ethernet, PCIe, CXL, AMBA).
SystemVerilog, UVM, Python, Perl, Tcl, shell, Cadence, Mentor, Synopsys
2mo
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SoC Platform Engineer
Saratoga, California, United States
$150k-$220k/yr OnsiteFull Time
Experience with IP integration, system verification, firmware for SoC; RTL, AMBA interconnects; C/Python scripting; ARM architecture.
SystemVerilog, VHDL, UVM, C, Python, Tcl, Bash, Makefiles, Git, VCS, Questa, Xcelium, JTAG
1mo
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SOC Intergration Engineer
Mountain View, California, United States
$120k-$600k/yr HybridFull Time
SystemVerilog; Python/Perl; experience integrating CPUs/GPUs/accelerators; SOC RTL; timing constraints; DV automation; emulation/verification familiarity.
SystemVerilog, Python, Perl, RTL design, DV tooling, Synthesis
1mo
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Performance Verification Engineer
Mountain View, California, United States
$200k-$350k/yr OnsiteFull Time
8+ YOEMaster's degree plus ~8 years experience in performance validation/verification of complex SoCs, performance modeling, debugging and correlation, tool-flow ownership, and collaboration with RTL designers and architects.
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