10 soc verification engineer jobs at 4 companies in Portland, OR
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SoC Verification Engineer
Austin or Santa Clara or Hillsboro
$142k-$200k/yr HybridFull Time
3+ YOE3+ years SoC design verification experience (4+ with bachelor's) with OVM/UVM, AMBA protocols, UVM testbench creation, debugging, and test planning; bachelor's or master's in EE/CE/CS or related.
OVM, UVM, CHI, AXI, AHB, APB, VIP, emulation models, system simulation tools
2mo
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SoC Physical Design Verification Engineer
Beaverton, Oregon, United States
OnsiteFull Time
Experience with physical verification of system-on-chip (SoC) designs and contributing to the design and manufacture of high-performance, power-efficient processors.
2mo
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SoC Physical Design Verification Engineer
Beaverton, Oregon, United States
OnsiteFull Time
Design and perform physical verification for SoC to ensure manufacturability and high performance; strong attention to detail and ability to work on complex semiconductor problems.
2mo
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Principal Silicon Design Verification Engineer
Santa Clara or Mountain View or Hillsboro or Austin or Boise or San Diego or Redmond
$143k-$275k/yr HybridFull Time
3+ YOEValidate PCIe IP using UVM testbenches, develop test plans, manage regressions, and meet coverage goals. Requires relevant degree plus 3–8+ years of technical engineering experience and ability to pass Microsoft security screening.
Verilog, System Verilog, UVM, UVM/C, PCIe, NVMe, RDMA, SoC
2mo
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SoC Physical Design Methodology Engineer
Beaverton, Oregon, United States
OnsiteFull Time
Design and verify high-performance, power-efficient system-on-chip (SoC) processors and perform physical verification for SoC products.
3mo
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Senior Testchip SoC Physical Design Engineer (Integration & Methodology)
Hillsboro or Santa Clara or Austin
$142k-$200k/yr HybridFull Time
5+ YOEMaster's degree in electrical engineering or related field; 5+ years in physical/layout design, advanced nodes; proficiency with layout tools; floorplanning and design verification.
Cadence Virtuoso Suite, Synopsys Custom Compiler
1mo
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CPU Design Methodology Engineer
Hillsboro or Austin or Santa Clara or Arizona
$136k-$265k/yr OnsiteFull Time
5+ YOEMasters in Computer or Electrical Engineering or equivalent,5+ years chip/SOC design experience,RTL/verification and design automation expertise,proficient in scripting (Perl/Python),strong analytical and interpersonal skills.
Verilog, UVM, System Verilog, Perl, Python
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CPU Design Methodology Engineer
Hillsboro or Austin or Arizona or Santa Clara
$168k-$311k/yr OnsiteFull Time
8+ YOEMaster's in computer or electrical engineering or equivalent experience; 8+ years in chip design focused on SoC integration and design automation; RTL, verification, scripting, synthesis, and physical design experience.
Verilog, Universal Verification Methodology (UVM), SystemVerilog, Perl, Python
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CPU Design Methodology Engineer
Hillsboro or Austin or Santa Clara or Arizona
$168k-$311k/yr HybridFull Time
8+ YOEMaster's in computer or electrical engineering or equivalent experience; 8+ years in chip design focused on SoC integration and design automation; RTL, verification, scripting, analytical, and problem-solving skills required.
Verilog, UVM, SystemVerilog, Perl, Python
4w
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Senior Silicon Engineer
Redmond or Mountain View or Santa Clara or Austin or Raleigh or Hillsboro or Boise
$120k-$235k/yr HybridFull Time
5+ YOEExperience verifying silicon using UVM/C, strong RTL and SoC verification background, proficiency with Verilog/System Verilog, and relevant EE/CS/CE degree or equivalent experience.
UVM, C, Verilog, System Verilog, Microsoft Excel