133 sta jobs at 42 companies in California
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STA Engineer
Santa Clara, California, United States
$153k-$230k/yr OnsiteFull Time
6+ YOE6+ years ASIC/SoC STA and synthesis experience with timing-closure, MMMC, low-power checks, SDC development, scripting (TCL/Perl), and hands-on use of PrimeTime and synthesis tools.
TCL, Perl, Python, Synopsys Prime Time, Synopsys Design Compiler, Cadence Genus, Conformal ECO Tool, PrimePower (PTPX)
2mo
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Senior SoC STA Engineer
San Diego, California, United States
OnsiteFull Time
10+ YOESenior SoC timing sign-off ownership; 10+ years in chip-level STA; Cadence Tempus; Python/Tcl scripting; strong cross-functional collaboration.
Cadence Tempus, Python, Tcl, DFT tools, CPDF/UPF tools
3mo
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Senior Static Timing Analysis (STA) Methodology Engineer
Saratoga, California, United States
$120k-$220k/yr OnsiteFull Time
8+ YOESenior STA/Timing methodology engineer with 8+ years in STA, scripting (Tcl/Python/Perl), signoff; BS/MS in ECE or related; onsite in Saratoga, CA.
PrimeTime, PT-SI, PT-PX, PT-ECO, Tcl, Python, Perl
1mo
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ASIC DFT STA Technical Lead
San Jose or Santa Clara
$169k-$241k/yr OnsiteFull Time
3+ YOEDegree with relevant years of experience (Bachelors+8/Masters+6/PhD+3). Experience with RTL design, CDC/RDC, conformal verification, SDC development, timing constraint development, and scripting (Perl, TCL, Python, Makefile).
Perl, TCL, Python, Makefile, Synopsys PrimeTime, Synopsys Fusion, Design Compiler, Tessent
1mo
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STA/Constraints Engineer
Santa Clara, California, United States
HybridFull Time
Experience in STA, timing signoff, and physical design; expert use of PD tools (SNPS PT/GCA, ICC2/FC); scripting with Perl/TCL/Shell/Python; Verilog RTL experience; strong communication; Bachelor/Master preferred.
SNPS PT, GCA, ICC2, FC, Perl, TCL, Shell, Python, Verilog, SDC
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ASIC Implementation Engineer STA
San Jose, California, United States
$144k-$230k/yr OnsiteFull Time
12+ YOEBachelor's in EE or Computer Engineering, 12+ years ASIC STA experience, proficiency with Cadence or Synopsys sign-off flows, SDC/constraint development, and scripting in Tcl, Python, or Perl.
Tcl, Python, Perl, Shell, Cadence, Synopsys
1mo
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Physical Design Implementation and STA Lead
San Jose, California, United States
$149k-$215k/yr OnsiteFull Time
7+ YOEBachelor's in EE/CE,7+ years physical design/implementation experience,3+ years STA with Synopsys PrimeTime,block-level implementation skills,Proficiency in Tcl and Python,mentoring and leadership experience.
Synopsys PrimeTime, Tcl, Python
2mo
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Principal Engineer, ASIC Design/Implementation - LEC/STA/Power Analysis
San Diego, California, United States
$160k-$237k/yr OnsiteFull Time
10+ YOEBachelor’s or higher in CS/EE; 10-15 years ASIC timing/STA; STA tooling and scripting; experience with advanced nodes (5nm/4nm); timing signoff and optimization.
Primetime, Tcl, Python, Perl
3w
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Static Timing Analysis Engineer, Full Chip STA
Mountain View, California, United States
$163k-$236k/yr OnsiteFull Time
8+ YOEBachelor's in EE/CS or equivalent,8+ years in silicon timing closure and chip integration, experience with PrimeTime/Tempus, STA signoff and constraint authoring, scripting with Tcl or Perl.
PrimeTime, Tempus, Tcl, Perl
3w
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SoC Static Timing Analysis (STA) Engineer, HBM
Folsom or Richardson
$199k-$347k/yr OnsiteFull Time
15+ YOE15+ years chip-level STA ownership at advanced nodes (5nm+), expertise with Synopsys PrimeTime or Cadence Tempus, deep timing methodology knowledge, and Python/Tcl scripting for automation.
Synopsys PrimeTime, Cadence Tempus, Python, Tcl
1w
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Static Timing Analysis (STA) Engineer – (Lead or Senior)
El Segundo, California, United States
$146k-$239k/yr OnsiteFull Time
5+ YOEBachelor's degree in a related technical field and 5+ years of ASIC/FPGA timing closure experience. Requires STA, synthesis, timing tools, scripting, and U.S. citizenship for security clearance.
Synopsys PrimeTime, Cadence Tempus, Synopsys Design Compiler, Cadence Genus, Python, TCL, Perl, Unix shell, Vivado, Synopsys Fusion Compiler, Formality, Cadence LEC, TCM, Fishtail, C shell
2mo
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Sr. Staff Physical Design Timing Engineer (STA)
Boston or Mountain View or Toronto
$217k-$267k/yr HybridFull Time
12+ YOEBachelor's in EE/CE, 12 years physical design experience (minimum 5 years hands-on ASIC STA/timing closure), experience with Cadence or Synopsys flows, Tempus/PrimeTime, scripting (TCL, Python, PERL, Shell), strong problem-solving and communication.
Tempus, PrimeTime, Cadence, Synopsys, TCL, Python, PERL, Shell
2mo
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Care Supervisor, Programs- STA
Arizona or Arkansas or California or Colorado or Florida or Kansas or Maryland or Missouri or Nevada or New Jersey or New York or North Carolina or Oregon or Pennsylvania or South Carolina or Tennessee or Texas or Washington or Wisconsin
$128k-$160k/yr RemoteFull Time
4+ YOE2+ MgmtRequires PharmD and active U.S. pharmacist license, 4+ years in high-volume pharmacy, 2+ years supervisory experience, program and project management, regulatory compliance, stakeholder management, and pharmacy systems proficiency.
G Suite, JIRA, Looker
2mo
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Principal Physical Design Engineer, STA
San Jose, California, United States
$209k-$250k/yr OnsiteFull Time
10+ YOE10+ years in timing analysis and sign-off for complex SoCs; Cadence/Synopsys flows; 7nm or below; scripting (Tcl/Python/Perl); able to work independently.
Cadence, Synopsys, Tcl, Python, Perl, SystemVerilog
1w
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Static Timing Analysis (STA) Engineer – (Lead or Senior)
El Segundo, California, United States
$146k-$239k/yr OnsiteFull Time
5+ YOEBachelor's degree in a relevant technical field, 5+ years timing closure experience on ASICs/FPGAs, ASIC tape-out experience, RTL-to-GDS knowledge, and proficiency with timing, synthesis, and scripting tools.
Synopsys Primetime, Cadence Tempus, Synopsys Design Compiler, Cadence Genus, Vivado, Synopsys Fusion Compiler, Formality, Cadence LEC, TCM, Fishtail, Python, TCL, Perl, Unix shell, C SHELL, RTL, GDS, ASIC, FPGA
2mo
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Senior ASIC Timing Engineer
Santa Clara or Durham or Austin or Hillsboro
$136k-$265k/yr HybridFull Time
3+ YOEBS in ECE + 5 years or MS + 3 years in timing/STA; hands-on full-chip and sub-chip STA, timing convergence, ECO implementation, physical design optimization, and deep sub-micron modeling.
STA, RTL, DFT, DFX, Formal Verification (FV)
6d
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Operations Agent
Carson, California, United States
$28-$32/hr OnsiteFull Time
3+ YOEHigh school diploma, 3+ years of freight forwarding, air freight, or domestic operations experience, ability to obtain a STA badge, drug test clearance, and Microsoft Office proficiency.
Microsoft Office, HAZMAT, IATA, DOT, STA
1mo
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Senior DFT Engineer
Santa Clara, California, United States
$136k-$265k/yr HybridFull Time
3+ YOEExperience in scan test, BIST, ATPG, fault simulation; strong scripting (Perl/Python/Tcl); cross-functional RTL, STA, PnR exposure; silicon bring-up and ATE experience.
Perl, Python, Tcl, ATPG, STA, ATE
1w
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Physcial Design Engineer
Mountain View, California, United States
$100k-$180k/yr OnsiteFull Time
8+ YOERequires 8–10 years of physical design and PnR experience, advanced-node expertise, and proficiency with floorplanning, CTS, routing, timing closure, STA, SDC, EMIR, PPA optimization, and EDA tools.
Synopsys Fusion Compiler, Synopsys ICC2, PrimeTime, Cadence Innovus, RedHawk, Voltus, GDSII, SDC, STA, EMIR
3d
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CALIFORNIA - PSE SALES & SVCS/DISTRIBUTION ASSOCIATE OCD-BROOKS ST STA - 2026-08-14
Oceanside, California, United States
$21/hr OnsiteFull Time, Temporary
Provides counter sales and customer support, processes purchases and returns, performs passport duties, arranges displays, and meets background, medical, and eligibility requirements.
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