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SoC Static Timing Analysis (STA) Engineer, HBM
Folsom or Richardson
$199k-$347k/yr OnsiteFull Time
15+ YOE15+ years chip-level STA ownership at advanced nodes (5nm+), expertise with Synopsys PrimeTime or Cadence Tempus, deep timing methodology knowledge, and Python/Tcl scripting for automation.
Synopsys PrimeTime, Cadence Tempus, Python, Tcl
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Senior Staff Digital Design Engineer
Plano, Texas, United States
HybridFull Time
5+ YOE5+ years in digital IC design with Verilog/SystemVerilog, RTL, synthesis, STA, verification, silicon debug, UVM and experience with industry EDA tools; B.Tech/M.Tech in electronics or related field.
Verilog/SystemVerilog, UVM, I²C, I3C, SPI, UART, Python, Tcl, Perl, Shell, Xcelium, Genus, SpyGlass, OneSpin/JasperGold, Innovus, PrimeTime/Tempus, DFT, ARM, AMBA (AXI/AHB/APB), Cadence Virtuoso, STA, LEC, Lint, Formal Verification
1mo
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Principal Engineer, Digital Design (IO Subsystem)
Allen, Texas, United States
OnsiteFull Time
onsemi: Designs and manufactures semiconductor solutions for power and sensing.
10+ YOEBachelor's in EE (Master's preferred), 10+ years digital IC/RTL design, expert SystemVerilog, Python, UVM, UPF/STA/timing signoff, DFT experience, and strong cross-functional collaboration.
SystemVerilog, Python, UVM, UPF, STA, DFT, AI/ML
1mo
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CAD Engineer
Richardson, Texas, United States
HybridFull Time
5+ YOEBachelor's in electrical engineering (or related) plus 5 years' relevant experience; proficiency with Verilog simulation, SPICE/logic simulators, PrimeTime STA, parasitic extraction, TSMC flows, and schematic/layout tools.
Electronic Design Automation (EDA), Verilog, spice simulators, logic simulators, PrimeTime, Parasitic Extraction tools, TSMC-based design and verification flows, Schematic and layout composers
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Design Infrastructure Engineer (Standard and Custom Cell Characterization)-HBM
Richardson, Texas, United States
OnsiteFull Time
Bachelors or Masters in EE, hands-on experience with standard/custom cell characterization, Liberty/SPICE-based simulation, STA flows, and scripting (Python/Perl/Tcl). Experience with SiliconSmart or PrimeLib required.
Liberty, CCS, ECSM, SPICE, STA, Python, Perl, Tcl, SiliconSmart, PrimeLib, Agentic AI
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Digital IC Design Engineer | Custom
Dallas, Texas, United States
OnsiteFull Time
8+ YOEBachelor's in EE/ECE/Computer Engineering, 8 years engineering experience including 3 years mixed-signal design verification, experience with Gates+SDF timing verification, automation scripting, and mixed-signal verification flows.
JasperGold, Gates+SDF, RTL, STA
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HBM SoC Physical Design Engineer
Richardson, Texas, United States
OnsiteFull Time
10+ YOEImplement SoC physical designs from netlist to GDSII; proficiency with industry EDA tools, STA/SDC, power-intent (UPF/CPF), physical verification, and timing/power signoff.
Cadence Innovus, Cadence Tempus, Synopsys ICC2, Synopsys PrimeTime, Siemens Calibre, GDSII, SDC, UPF, CPF
1mo
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Staff Digital Design Engineer, HBM
Richardson, Texas, United States
OnsiteFull Time
3+ YOEBachelor's in EE (or equivalent) with 3+ years experience; RTL design in Verilog/SystemVerilog, synthesis/STA, CDC analysis, low-power methodologies, Linux and scripting (Python/Perl); strong digital logic and architecture skills.
Verilog, SystemVerilog, Linux, Python, Perl, CPF, UPF, SDC, AMBA, AXI, APB
2mo
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HBM SoC Physical Design Engineer
Richardson, Texas, United States
OnsiteFull Time
10+ YOESoC physical design from netlist to GDSII; strong EDA/tool skills; STA; DRC/LVS; UPF/CPF; 10+ yrs; memory/HBM exp preferred; Bachelors/Masters in EE/CE.
Cadence Innovus, Cadence Tempus, Synopsys ICC2, Synopsys PrimeTime, Siemens Calibre, UPF/CPF
2mo
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Staff Wireless IC Digital Designer
Dallas, Texas, United States
OnsiteFull Time
8+ YOESenior level design engineer with 8-12 years in digital RF/wireless design, IC/SoC development, RTL, and verification.
RTL, Synthesis, STA, ATPG, RFIC, SoC, Digital design, FPGA design