3d
Save
Mark Applied
Hide
STA Engineer
Fort Collins, Colorado, United States
$129k-$207k/yr OnsiteFull Time
10+ YOEDeep STA and timing-closure expertise for large SoC designs, strong timing analysis, familiarity with noise/cross-talk/OCV, circuit modeling, Perl/TCL scripting; MSEE and extensive industry experience.
STA, Perl, TCL, SPICE
3mo
Save
Mark Applied
Hide
STA Engineer
Austin or Cupertino
OnsiteFull Time
0+ YOEBachelor's degree required; 0 years experience; strong Digital design fundamentals; scripting, STA tools familiarity.
Primetime, TCL, Python, Perl, Synthesis, Logic Equivalence Checks
2w
Save
Mark Applied
Hide
STA Engineer
Santa Clara, California, United States
$153k-$230k/yr OnsiteFull Time
6+ YOE6+ years ASIC/SoC STA and synthesis experience with timing-closure, MMMC, low-power checks, SDC development, scripting (TCL/Perl), and hands-on use of PrimeTime and synthesis tools.
TCL, Perl, Python, Synopsys Prime Time, Synopsys Design Compiler, Cadence Genus, Conformal ECO Tool, PrimePower (PTPX)
3w
Save
Mark Applied
Hide
Raptor STA Engineer
Allen Park, Michigan, United States
$87k-$166k/yr HybridFull Time
7+ YOEBachelor's in engineering, 7+ years plant-floor manufacturing and STA experience, APQP/PPAP knowledge, strong communication and quality/risk assessment skills, ability to travel ~33%.
1w
Save
Mark Applied
Hide
Senior STA Engineer
Austin, Texas, United States
$152k-$217k/yr OnsiteFull Time
5+ YOE5+ years STA on high-performance CPU designs, expert multi-scenario STA/SDC, OCV/AOCV/POCV margining, Tempus/PrimeTime proficiency, scripting in Tcl/Python/Perl, advanced-node tape-out experience.
Cadence Tempus, Synopsys PrimeTime, Tcl, Python, Perl, ETM, Hyperscale
3w
Save
Mark Applied
Hide
Raptor STA Engineer
Allen Park, Michigan, United States
$87k-$166k/yr HybridFull Time
7+ YOEBachelor's in engineering, 7+ years plant-floor manufacturing quality/manufacturing engineering, 7+ years STA program/launch experience, APQP/PPAP knowledge, strong communication, ability to travel ~33%.
2mo
Save
Mark Applied
Hide
Senior SoC STA Engineer
San Diego, California, United States
OnsiteFull Time
10+ YOESenior SoC timing sign-off ownership; 10+ years in chip-level STA; Cadence Tempus; Python/Tcl scripting; strong cross-functional collaboration.
Cadence Tempus, Python, Tcl, DFT tools, CPDF/UPF tools
2mo
Save
Mark Applied
Hide
Senior Static Timing Analysis (STA) Methodology Engineer
Saratoga, California, United States
$120k-$220k/yr OnsiteFull Time
8+ YOESenior STA/Timing methodology engineer with 8+ years in STA, scripting (Tcl/Python/Perl), signoff; BS/MS in ECE or related; onsite in Saratoga, CA.
PrimeTime, PT-SI, PT-PX, PT-ECO, Tcl, Python, Perl
3w
Save
Mark Applied
Hide
ASIC DFT STA Engineer
San Jose or Santa Clara
$165k-$241k/yr OnsiteFull Time
1+ YOEDegree plus relevant years of experience (BSc+7 / MSc+4 / PhD+1). Experience with RTL, CDC/RDC, conformal verification, SDC development, timing constraint development, and scripting (Perl, Tcl, Python, Makefile).
Perl, Tcl, Python, Makefile, Synopsys TCM, Synopsys PrimeTime, Synopsys Fusion, Synopsys Design Compiler, Tessent, Conformal
1w
Save
Mark Applied
Hide
STA/Constraints Engineer
Santa Clara, California, United States
HybridFull Time
Experience in STA, timing signoff, and physical design; expert use of PD tools (SNPS PT/GCA, ICC2/FC); scripting with Perl/TCL/Shell/Python; Verilog RTL experience; strong communication; Bachelor/Master preferred.
SNPS PT, GCA, ICC2, FC, Perl, TCL, Shell, Python, Verilog, SDC
1mo
Save
Mark Applied
Hide
Static Timing Analysis (STA) Engineer
Tukwila or El Segundo
$146k-$239k/yr OnsiteFull Time
5+ YOEB.S. degree, 5+ years timing closure experience on ASICs/FPGAs, ability to obtain U.S. security clearance, proficiency with STA tools and scripting (Python, Tcl, Perl).
Synopsys PrimeTime, Cadence Tempus, Synopsys Design Compiler, Cadence Genus, Xilinx Vivado, Synopsys Fusion Compiler, Formality (Cadence LEC), TCM, Fishtail, Python, Tcl, Perl, Unix shell, C Shell
1mo
Save
Mark Applied
Hide
Principal Engineer, ASIC Design/Implementation - LEC/STA/Power Analysis
San Diego, California, United States
$160k-$237k/yr OnsiteFull Time
10+ YOEBachelor’s or higher in CS/EE; 10-15 years ASIC timing/STA; STA tooling and scripting; experience with advanced nodes (5nm/4nm); timing signoff and optimization.
Primetime, Tcl, Python, Perl
3mo
Save
Mark Applied
Hide
Principal (STA/ Sign-Off) Engineer-17042 (Austin/ Sunnyvale)
Sunnyvale or Austin
$191k-$286k/yr OnsiteFull Time
12+ YOEBS/MS in Electrical Engineering, 12+ years developing CAD flows for high-speed digital IP/SOCs, hands-on STA and EM/IR signoff experience, familiarity with Synopsys tools (StarRC, ICV), strong communication and problem-solving.
Static Timing Analysis (STA), EM/IR, StarRC, ICV, PDK
3d
Save
Mark Applied
Hide
SoC Static Timing Analysis (STA) Engineer, HBM
Folsom or Richardson
$199k-$347k/yr OnsiteFull Time
15+ YOE15+ years chip-level STA ownership at advanced nodes (5nm+), expertise with Synopsys PrimeTime or Cadence Tempus, deep timing methodology knowledge, and Python/Tcl scripting for automation.
Synopsys PrimeTime, Cadence Tempus, Python, Tcl
3d
Save
Mark Applied
Hide
SoC Static Timing Analysis (STA) Engineer, HBM
Folsom or Richardson
$199k-$347k/yr OnsiteFull Time
15+ YOE15+ years chip-level STA and sign-off experience at advanced nodes, expertise with Synopsys PrimeTime/Cadence Tempus, deep timing methodology knowledge, and Python/Tcl scripting for flow automation.
Synopsys PrimeTime, Cadence Tempus, Python, Tcl, Synopsys Design Constraints (SDC)
1mo
Save
Mark Applied
Hide
Sr. Staff Physical Design Timing Engineer (STA)
Boston or Mountain View or Toronto
$217k-$267k/yr HybridFull Time
12+ YOEBachelor's in EE/CE, 12 years physical design experience (minimum 5 years hands-on ASIC STA/timing closure), experience with Cadence or Synopsys flows, Tempus/PrimeTime, scripting (TCL, Python, PERL, Shell), strong problem-solving and communication.
Tempus, PrimeTime, Cadence, Synopsys, TCL, Python, PERL, Shell
1mo
Save
Mark Applied
Hide
Static Timing Analysis (STA) Engineer
Tukwila or El Segundo
$146k-$239k/yr OnsiteFull Time
5+ YOEAbility to obtain U.S. security clearance, BS in engineering/math/CS (or equivalent), 5+ years timing closure experience on ASICs/FPGAs, proficiency with PrimeTime/Tempus and Design Compiler/Genus, scripting (Python/TCL/Perl/Unix shell).
Synopsys PrimeTime, Cadence Tempus, Synopsys Design Compiler, Cadence Genus, Synopsys Fusion Compiler, Formality (Cadence LEC), Vivado, Python, TCL, Perl, Unix shell, TCM, Fishtail, GDS
2mo
Save
Mark Applied
Hide
Principal Physical Design Engineer, STA
San Jose, California, United States
$209k-$250k/yr OnsiteFull Time
10+ YOE10+ years in timing analysis and sign-off for complex SoCs; Cadence/Synopsys flows; 7nm or below; scripting (Tcl/Python/Perl); able to work independently.
Cadence, Synopsys, Tcl, Python, Perl, SystemVerilog
1w
Save
Mark Applied
Hide
Physical Design Implementation and STA Lead
San Jose, California, United States
$149k-$215k/yr OnsiteFull Time
7+ YOEBachelor's in EE/CE,7+ years physical design/implementation experience,3+ years STA with Synopsys PrimeTime,block-level implementation skills,Proficiency in Tcl and Python,mentoring and leadership experience.
Synopsys PrimeTime, Tcl, Python
1mo
Save
Mark Applied
Hide
Senior ASIC Timing Engineer
Santa Clara or Durham or Austin or Hillsboro
$136k-$265k/yr HybridFull Time
3+ YOEBS in ECE + 5 years or MS + 3 years in timing/STA; hands-on full-chip and sub-chip STA, timing convergence, ECO implementation, physical design optimization, and deep sub-micron modeling.
STA, RTL, DFT, DFX, Formal Verification (FV)
Explore Jobs