3mo
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STA Engineer
Austin or Cupertino
OnsiteFull Time
0+ YOEBachelor's degree required; 0 years experience; strong Digital design fundamentals; scripting, STA tools familiarity.
Primetime, TCL, Python, Perl, Synthesis, Logic Equivalence Checks
1w
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Senior STA Engineer
Austin, Texas, United States
$152k-$217k/yr OnsiteFull Time
5+ YOE5+ years STA on high-performance CPU designs, expert multi-scenario STA/SDC, OCV/AOCV/POCV margining, Tempus/PrimeTime proficiency, scripting in Tcl/Python/Perl, advanced-node tape-out experience.
Cadence Tempus, Synopsys PrimeTime, Tcl, Python, Perl, ETM, Hyperscale
3mo
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Principal (STA/ Sign-Off) Engineer-17042 (Austin/ Sunnyvale)
Sunnyvale or Austin
$191k-$286k/yr OnsiteFull Time
12+ YOEBS/MS in Electrical Engineering, 12+ years developing CAD flows for high-speed digital IP/SOCs, hands-on STA and EM/IR signoff experience, familiarity with Synopsys tools (StarRC, ICV), strong communication and problem-solving.
Static Timing Analysis (STA), EM/IR, StarRC, ICV, PDK
1mo
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Senior ASIC Timing Engineer
Santa Clara or Durham or Austin or Hillsboro
$136k-$265k/yr HybridFull Time
3+ YOEBS in ECE + 5 years or MS + 3 years in timing/STA; hands-on full-chip and sub-chip STA, timing convergence, ECO implementation, physical design optimization, and deep sub-micron modeling.
STA, RTL, DFT, DFX, Formal Verification (FV)
3w
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CPU Physical Design Timing Engineer (Austin, TX)
Austin, Texas, United States
$123k-$184k/yr OnsiteFull Time
2+ YOEBachelor's in EE/CE/CS with 2+ years (or Master's with 1+ year, or PhD) and experience in STA timing closure, automation scripting (TCL/Perl/Python), PrimeTime/Tempus, ICC/Innovus, and STA signoff for multi-mode/multi-voltage CPU designs.
TCL, Perl, Python, PrimeTime, Tempus, PT, ICC, Innovus, Spice, STA
1mo
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Physical Design Engineer
San Jose or Austin
$165k-$241k/yr OnsiteFull Time
1+ YOEBachelor’s/Master’s/PhD in Electrical or Computer Engineering with ASIC RTL-to-GDSII experience for advanced nodes; experience with Innovus, Tempus/PrimeTime, Redhawk/Voltus, Calibre/Pegasus, Python, and STA.
Innovus, Tempus, PrimeTime, Redhawk, Voltus, Calibre, Pegasus, Tweaker, Python
2mo
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CPU Circuit Design Engineer
Austin, Texas, United States
$142k-$269k/yr HybridFull Time
5+ YOEBachelor's/Master's in Electrical/Computer Engineering; 5+ years CPU circuit/backend design; 5+ years circuit design and STA; strong PPA tradeoff and debug skills.
Verilog, SPICE, Timing Analysis, Circuit Simulation
1d
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Senior Silicon Engineer
Redmond or Austin or Raleigh or Hillsboro
$120k-$235k/yr HybridFull Time
1+ YOEDegree in EE/CE/CS or equivalent with 1–5+ years technical engineering experience depending on degree; expertise in RTL, synthesis, STA, PD flows; proficiency in Tcl and Python; ability to pass Microsoft cloud background and export-control screenings.
PrimeTime, Genus, DC, Innovus, ICC2, Tcl, Python
19h
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ASIC Engineer, Implementation - Timing
Sunnyvale or Austin
$146k-$209k/yr OnsiteFull Time
6+ YOEBachelor's degree or equivalent,6+ years timing analysis experience, STA and timing-constraint development, knowledge of front-end and back-end ASIC flows, and cross-team communication skills.
PrimeTime, DMSA, Fusion Compiler, Innovus, Design Compiler, Genus
2mo
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Physical Design Engineer, PnR
Austin or Fort Collins or Santa Clara
$100k-$500k/yr HybridFull Time
Synthesize, PNR, and STA for AI SoC partitions; use Synopsys tools; collaborate in a small PD team; knowledge of UPF/power domains and IP integration is a plus.
Synopsys Design Compiler, Fusion Compiler, IC Compiler II, Power domain tools, LEC/Formality, DRC/LVS, EM/IR, UPF, DFT (OCC/MBIST)
3mo
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ASIC RTL Design Engineer (784246)
Austin, Texas, United States
HybridFull Time
3+ YOEBS in Electrical or Computer Engineering; several years of hands-on RTL design experience; strong digital logic; proficient in C/C++, TCL, Python; SystemVerilog/Verilog/VHDL; CDC/STA knowledge; RTL linting/CDC tools; AMBA experience; EDA tool familiarity; Git/Linux.
SystemVerilog, Verilog, VHDL, C, C++, Python, TCL, EDA tools, SpyGlass, AMBA, Cadence, Mentor, Synopsys, Git, Linux
1mo
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Senior Digital Design Engineer
Austin, Texas, United States
OnsiteFull Time
4+ YOEBachelors in EE/CE/CS required, 4+ years IP or SoC design experience, expert Verilog, knowledge of SoC architecture, experience with Lint/CDC/STA, ARM AMBA desired; C and scripting (Perl/Python) and functional safety are a plus.
Verilog, System Verilog, Lint, CDC, Static Timing Analysis (STA), ARM AMBA, C, Perl, Python
2d
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Senior ASIC Physical Design Engineer, Netlisting
Santa Clara or Austin
$136k-$265k/yr HybridFull Time
3+ YOE5+ years (BS) or 3+ years (MS) experience in physical ASIC design, expertise in equivalence checking/FV, RTL/logic design, CDC/MTBF analysis, logic synthesis, STA and timing convergence, and scripting/programming skills.
Perl, TCL, Make, Python, Static Timing Analysis (STA)
1mo
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Digital Design Verification Engineer
Bristol or Austin
£125k/yr OnsiteFull Time
5+ YOE5+ years in digital verification for high-performance ASICs/SoCs; strong SystemVerilog, SVA, UVM, Cocotb, formal verification, CDC/RDC, and algorithm modelling (MATLAB/Simulink or Python/NumPy) skills; experience with high-speed IP (SerDes, DDR/HBM, PCIe).
SystemVerilog, UVM, SVA, CocoTB, MATLAB/Simulink, Python, NumPy, Jasper, FPGA, RTL simulation, formal verification, linting, CDC/RDC, STA, UPF, CPF, gate-level simulation
2mo
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Member of Technical Staff, Hardware, Physical Design Engineer
Palo Alto or Austin
$200k-$420k/yr OnsiteFull Time
5+ YOEBachelor's in EE/CE and 5+ years with advanced process nodes (7nm or below); hands-on experience with physical design, synthesis, P&R, STA, sign-off flows, UPF/CPF power intent, and scripting (Tcl/Python).
Innovus, Fusion Compiler, PrimeTime, RedHawk, Unified Power Format (UPF), Common Power Format (CPF), Tcl, Python
2mo
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Lead RTL Design Engineer
Austin or Pittsburgh or San Jose
$160k-$250k/yr OnsiteFull Time
8+ YOE8+ years RTL design with tape-out ownership; SystemVerilog; on-chip networks, memory subsystems, NoC; low-power design; DV collaboration; silicon bring-up.
SystemVerilog, UPF, AXI, AHB, APB, TileLink, NoC, SDC, STA, ATPG, DFT, memory compiler
1mo
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Physical Design Engineer - Static Timing Analysis, Annapurna Labs, Cloud Scale Machine Learning
Cupertino or Austin
$136k-$213k/yr OnsiteFull Time
1+ YOEDegree in EE/CS with relevant experience (BS+6 / MS+4 / PhD+2), 1+ years STA and timing constraint development, scripting (Tcl/Perl/Python), timing analysis fundamentals, familiarity with PrimeTime/Tempus and RTL-to-GDSII physical design flow.
PrimeTime, Tempus, PT-DMSA, Tempus-ECO, Tweaker, STAR-RC, Quantus, SPICE, SPECTRE, Tcl, Perl, Python
2mo
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Design Engineering Architect
Austin, Texas, United States
OnsiteFull Time
10+ YOE10+ years front end design/verification; leadership; IP/SoC integration; RTL design in Verilog/SystemVerilog/VHDL; Synthesis; PD/STA support; Cadence front end tools.
Verilog, SystemVerilog, VHDL, Cadence Front End toolset, Synthesis, PD and STA tools
1mo
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Micro-architect/Logic Designer, Coherent Interconnect
San Jose or Austin
$151k-$252k/yr OnsiteFull Time
6+ YOE6+ years experience in RTL and microarchitecture for coherent interconnects/LLC; Verilog expertise; strong ASIC design flow knowledge; experience with AMBA/AXI/CHI protocols; leadership and collaboration skills.
Verilog, VHDL, Perl, Python, STA, DFT, ECO, AMBA5 CHI, AMBA4 ACE, AXI