1mo
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Sr. Staff Physical Design Timing Engineer (STA)
Boston or Mountain View or Toronto
$217k-$267k/yr HybridFull Time
12+ YOEBachelor's in EE/CE, 12 years physical design experience (minimum 5 years hands-on ASIC STA/timing closure), experience with Cadence or Synopsys flows, Tempus/PrimeTime, scripting (TCL, Python, PERL, Shell), strong problem-solving and communication.
Tempus, PrimeTime, Cadence, Synopsys, TCL, Python, PERL, Shell
1mo
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SoC Physical Design Engineer, STA/Timing
Waltham, Massachusetts, United States
OnsiteFull Time
Responsible for physical implementation of design partitions from netlist to tapeout for complex SoC using state-of-the-art process technology.
2mo
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ASIC Physical Design Engineer
Maynard or Austin
$136k-$195k/yr HybridFull Time
5+ YOEBachelors in Engineering with 5+ years or Masters in Engineering with 3+ years in ASIC physical design; experience with floorplanning, place-and-route, STA, timing closure, DFT collaboration, scripting, and design flow optimization.
Cadence Innovus, Synopsys ICC2, Synopsys DC/FC, Synopsys Formality, Cadence LEC, Tempus, Python, TCL, Perl
3w
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Physical Design Engineer
Massachusetts or Phoenix
$91k-$149k/yr OnsiteFull Time
0+ YOEDesign and implement physical IC/SoC from RTL to GDS, perform synthesis/place-and-route/CTS/STA, power and noise analysis, verification and optimization using EDA tools.
EDA tools, TCL
2w
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Mixed Signal Logic Design Engineer
Hillsboro or Santa Clara or Austin or Massachusetts
$164k-$232k/yr HybridFull Time
4+ YOEExpert-level Verilog/SystemVerilog RTL design, digital logic and RTL-to-GDSII flow knowledge; 4+ years industry experience (Master's) or 7+ years (Bachelor's); mixed-signal integration and debugging skills.
Verilog, SystemVerilog, EDA tools, Perl, TCL/Tk, Python, STA