3mo
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Principal Digital Design Engineer
Chandler or Vancouver or Remote
$200k-$250k/yr HybridFull Time
10+ YOEBachelor's or master's in electrical/computer engineering; 10+ years in digital design with RTL; SoC/subsystem tapeout experience; strong RTL, microarchitecture, back-end flows, DFT/scan, LEC, STA, SDC skills; solid timing, power, and debug expertise.
Synopsys, Cadence, EDA tools, Synthesis, DFT, LEC, STA, SDC, UPF/CPF, RTL
3mo
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Staff Engineer, Digital Design Engineering
Chandler or Spain or France
OnsiteFull Time
8+ YOERTL digital design; Verilog/SystemVerilog; Synthesis/STA/EDA tools; scripting (Python, Tcl, shell); AI/ML in design workflows; 8+ years in electrical/computer engineering.
Verilog, SystemVerilog, Python, Tcl, Shell, EDA tools
2w
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Physical Design Engineer
Massachusetts or Phoenix
$91k-$149k/yr OnsiteFull Time
0+ YOEDesign and implement physical IC/SoC from RTL to GDS, perform synthesis/place-and-route/CTS/STA, power and noise analysis, verification and optimization using EDA tools.
EDA tools, TCL
2mo
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Senior Digital Design Engineer
Chandler, Arizona, United States
OnsiteFull Time
3+ YOEMaster's degree in Electrical Engineering with emphasis on Digital Design; 3+ years in digital design/architecture; willing to relocate to Chandler/Phoenix area; strong problem solving and teamwork.
Verilog, SystemVerilog, HDL, Synthesis, STA, DFT
2w
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Senior Digital Engineer
Chandler, Arizona, United States
OnsiteFull Time
5+ YOE5+ years digital design experience, degree in electrical/computer discipline, fluent Verilog/SystemVerilog, ASIC methodology, lint/CDC/RDC experience, RTL and gate-level debug, English proficiency, willing to travel.
Verilog, SystemVerilog, Lint, CDC, RDC, UPF, UVM, AMBA, I2C, STA
1mo
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Staff Digital Design Engineer (AI/ML)
Chandler, Arizona, United States
OnsiteFull Time
5+ YOEMS (EE/CE) with 7+ years or PhD with 5+ years (BSEE/BSCE considered); strong Verilog/SystemVerilog RTL and tape-out experience; Python/Tcl/shell scripting; Cadence Genus/Innovus/Tempus/Conformal; synthesis, STA, DFT knowledge.
Verilog, SystemVerilog, Python, Tcl, Shell, Genus, Innovus, Tempus, Conformal
3w
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Sr Advanced Semiconductor Engineer
Phoenix or Glendale
HybridFull Time
5+ YOEBachelor's in a technical discipline, familiarity with VHDL/Verilog/SystemVerilog, 5+ years FPGA design/verification experience, and strong oral/written communication skills.
VHDL, Verilog, SystemVerilog, MATLAB, Simulink, LabVIEW, Perl, Shell, TCL, AMBA, I2C, SPI, Windows, LINUX, Microsoft Office, C, Xilinx, STA tools, Place & Route, synthesis
1w
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Staff Digital Design Engineer
Chandler, Arizona, United States
HybridFull Time
11+ YOE>10 years digital design experience, degree in EE/CE/CS or related, fluent Verilog/SystemVerilog, ASIC methodology knowledge, Lint/CDC/RDC experience, RTL and gate-level debug, English proficiency, travel readiness.
Verilog, SystemVerilog, Lint, CDC, RDC, UPF, UVM, AMBA, I2C, STA
4d
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Director, Digital Design & Verification
Chandler, Arizona, United States
OnsiteFull Time
Proven leader in digital IC design and verification for mixed-signal SoCs with expertise in RTL, verification methodologies (UVM, formal, AMS/DMS), architecture, and team building.
SystemVerilog, UVM, Formal, AMS/DMS, RTL, STA, DFT