3mo
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STA Engineer
Austin or Cupertino
OnsiteFull Time
0+ YOEBachelor's degree required; 0 years experience; strong Digital design fundamentals; scripting, STA tools familiarity.
Primetime, TCL, Python, Perl, Synthesis, Logic Equivalence Checks
1w
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Senior STA Engineer
Austin, Texas, United States
$152k-$217k/yr OnsiteFull Time
5+ YOE5+ years STA on high-performance CPU designs, expert multi-scenario STA/SDC, OCV/AOCV/POCV margining, Tempus/PrimeTime proficiency, scripting in Tcl/Python/Perl, advanced-node tape-out experience.
Cadence Tempus, Synopsys PrimeTime, Tcl, Python, Perl, ETM, Hyperscale
6d
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SoC Static Timing Analysis (STA) Engineer, HBM
Folsom or Richardson
$199k-$347k/yr OnsiteFull Time
15+ YOE15+ years chip-level STA ownership at advanced nodes (5nm+), expertise with Synopsys PrimeTime or Cadence Tempus, deep timing methodology knowledge, and Python/Tcl scripting for automation.
Synopsys PrimeTime, Cadence Tempus, Python, Tcl
6d
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SoC Static Timing Analysis (STA) Engineer, HBM
Folsom or Richardson
$199k-$347k/yr OnsiteFull Time
15+ YOE15+ years chip-level STA and sign-off experience at advanced nodes, expertise with Synopsys PrimeTime/Cadence Tempus, deep timing methodology knowledge, and Python/Tcl scripting for flow automation.
Synopsys PrimeTime, Cadence Tempus, Python, Tcl, Synopsys Design Constraints (SDC)
3mo
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Principal (STA/ Sign-Off) Engineer-17042 (Austin/ Sunnyvale)
Sunnyvale or Austin
$191k-$286k/yr OnsiteFull Time
12+ YOEBS/MS in Electrical Engineering, 12+ years developing CAD flows for high-speed digital IP/SOCs, hands-on STA and EM/IR signoff experience, familiarity with Synopsys tools (StarRC, ICV), strong communication and problem-solving.
Static Timing Analysis (STA), EM/IR, StarRC, ICV, PDK
3mo
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Supported Home Living Sta
Conroe, Texas, United States
$10/hr OnsiteFull Time
Assist individuals with daily living, safety, and mobility; follow PDP; document activities; perform health tasks; CPR.
1mo
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Care Supervisor, Programs- STA
Arizona or Arkansas or California or Colorado or Florida or Kansas or Maryland or Missouri or Nevada or New Jersey or New York or North Carolina or Oregon or Pennsylvania or South Carolina or Tennessee or Texas or Washington or Wisconsin
$128k-$160k/yr RemoteFull Time
4+ YOE2+ MgmtRequires PharmD and active U.S. pharmacist license, 4+ years in high-volume pharmacy, 2+ years supervisory experience, program and project management, regulatory compliance, stakeholder management, and pharmacy systems proficiency.
G Suite, JIRA, Looker
1mo
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Senior ASIC Timing Engineer
Santa Clara or Durham or Austin or Hillsboro
$136k-$265k/yr HybridFull Time
3+ YOEBS in ECE + 5 years or MS + 3 years in timing/STA; hands-on full-chip and sub-chip STA, timing convergence, ECO implementation, physical design optimization, and deep sub-micron modeling.
STA, RTL, DFT, DFX, Formal Verification (FV)
4w
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CPU Physical Design Timing Engineer (Austin, TX)
Austin, Texas, United States
$123k-$184k/yr OnsiteFull Time
2+ YOEBachelor's in EE/CE/CS with 2+ years (or Master's with 1+ year, or PhD) and experience in STA timing closure, automation scripting (TCL/Perl/Python), PrimeTime/Tempus, ICC/Innovus, and STA signoff for multi-mode/multi-voltage CPU designs.
TCL, Perl, Python, PrimeTime, Tempus, PT, ICC, Innovus, Spice, STA
5d
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Senior Staff Digital Design Engineer
Plano, Texas, United States
HybridFull Time
5+ YOE5+ years in digital IC design with Verilog/SystemVerilog, RTL, synthesis, STA, verification, silicon debug, UVM and experience with industry EDA tools; B.Tech/M.Tech in electronics or related field.
Verilog/SystemVerilog, UVM, I²C, I3C, SPI, UART, Python, Tcl, Perl, Shell, Xcelium, Genus, SpyGlass, OneSpin/JasperGold, Innovus, PrimeTime/Tempus, DFT, ARM, AMBA (AXI/AHB/APB), Cadence Virtuoso, STA, LEC, Lint, Formal Verification
1mo
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Principal Engineer, Digital Design (IO Subsystem)
Allen, Texas, United States
OnsiteFull Time
onsemi: Designs and manufactures semiconductor solutions for power and sensing.
10+ YOEBachelor's in EE (Master's preferred), 10+ years digital IC/RTL design, expert SystemVerilog, Python, UVM, UPF/STA/timing signoff, DFT experience, and strong cross-functional collaboration.
SystemVerilog, Python, UVM, UPF, STA, DFT, AI/ML
2mo
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Technology Projects Student Technology Assistant (STA 1) (Open to work study and non-work study)
Austin, Texas, United States
OnsitePart Time, Temporary
Current student; organized; detail-oriented; follows processes; able to perform physical and task-based work; willing to work on technology projects.
Inventory systems, Spreadsheets, Asset tracking
2mo
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Physical Design Engineer, PnR
Austin or Fort Collins or Santa Clara
$100k-$500k/yr HybridFull Time
Synthesize, PNR, and STA for AI SoC partitions; use Synopsys tools; collaborate in a small PD team; knowledge of UPF/power domains and IP integration is a plus.
Synopsys Design Compiler, Fusion Compiler, IC Compiler II, Power domain tools, LEC/Formality, DRC/LVS, EM/IR, UPF, DFT (OCC/MBIST)
2mo
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CPU Circuit Design Engineer
Austin, Texas, United States
$142k-$269k/yr HybridFull Time
5+ YOEBachelor's/Master's in Electrical/Computer Engineering; 5+ years CPU circuit/backend design; 5+ years circuit design and STA; strong PPA tradeoff and debug skills.
Verilog, SPICE, Timing Analysis, Circuit Simulation
1mo
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Physical Design Engineer
San Jose or Austin
$165k-$241k/yr OnsiteFull Time
1+ YOEBachelor’s/Master’s/PhD in Electrical or Computer Engineering with ASIC RTL-to-GDSII experience for advanced nodes; experience with Innovus, Tempus/PrimeTime, Redhawk/Voltus, Calibre/Pegasus, Python, and STA.
Innovus, Tempus, PrimeTime, Redhawk, Voltus, Calibre, Pegasus, Tweaker, Python
6d
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Sit Down Forklift
Grapevine, Texas, United States
$19-$21/hr OnsiteFull Time
1+ YOEPrior sit-down forklift experience, RF scanner and label-printing experience, able to lift heavy loads, English proficiency, reliable transportation, pass drug/background/STA checks.
RF scanners
3mo
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Design Engineering Architect
Austin, Texas, United States
OnsiteFull Time
10+ YOE10+ years front end design/verification; leadership; IP/SoC integration; RTL design in Verilog/SystemVerilog/VHDL; Synthesis; PD/STA support; Cadence front end tools.
Verilog, SystemVerilog, VHDL, Cadence Front End toolset, Synthesis, PD and STA tools
3d
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ASIC Engineer, Implementation - Timing
Sunnyvale or Austin
$146k-$209k/yr OnsiteFull Time
6+ YOEBachelor's degree or equivalent,6+ years timing analysis experience, STA and timing-constraint development, knowledge of front-end and back-end ASIC flows, and cross-team communication skills.
PrimeTime, DMSA, Fusion Compiler, Innovus, Design Compiler, Genus
18h
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Infrastructure and Tools Developer (787687)
Austin, Texas, United States
HybridFull Time
Hands-on experience with ASIC/SoC design, RTL, Verilog, UVM/SystemVerilog, front-end EDA tools, synthesis/STA/DFT, and scripting (Perl, Python, bash, csh). Strong communication and presentation skills.
Verilog, UVM, SystemVerilog, Perl, Python, bash, csh, CloudBees Jenkins, Load Sharing Facility (LSF), Slurm, Altair
18h
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Infrastructure and Tools Developer
Austin, Texas, United States
OnsiteFull Time
Several years of ASIC/SoC frontend experience with RTL/Verilog/SystemVerilog,UVM; scripting in Perl/Python/bash/csh; familiarity with synthesis, STA, DFT and front-end verification tools; BS/MS in EE/CS.
Verilog, UVM, SystemVerilog, Perl, Python, bash, csh, CloudBees Jenkins, LSF (Load Sharing Facility), Slurm, Altair
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