1 static timing analysis engineer job at 1 company in Arizona
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Principal FPGA Digital Engineer - 3
Chandler, Arizona, United States
$108k-$162k/yr OnsiteFull Time
5+ YOEBachelor's in EE/CE (or MS/PhD) with relevant FPGA/SoC design experience, expertise in VHDL/Verilog and Xilinx toolflow, static timing analysis, bus interfaces, simulation/verification, and ability to obtain DoD Secret clearance.
VHDL, Verilog, AMD Xilinx FPGAs, Vivado IDE, Vitis Unified IDE, Questa/ModelSim, OSVVM, UVM, AXI4, Ethernet, PCIe, UART, SDLC, DDR3, DDR4, DDR5, logic analyzer, oscilloscope, C, C++