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Static Timing Analysis (STA) Engineer
Tukwila or El Segundo
$146k-$239k/yr OnsiteFull Time
5+ YOEAbility to obtain U.S. security clearance, BS in engineering/math/CS (or equivalent), 5+ years timing closure experience on ASICs/FPGAs, proficiency with PrimeTime/Tempus and Design Compiler/Genus, scripting (Python/TCL/Perl/Unix shell).
Synopsys PrimeTime, Cadence Tempus, Synopsys Design Compiler, Cadence Genus, Synopsys Fusion Compiler, Formality (Cadence LEC), Vivado, Python, TCL, Perl, Unix shell, TCM, Fishtail, GDS
1mo
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Static Timing Analysis (STA) Engineer
Tukwila or El Segundo
$146k-$239k/yr OnsiteFull Time
5+ YOEB.S. degree, 5+ years timing closure experience on ASICs/FPGAs, ability to obtain U.S. security clearance, proficiency with STA tools and scripting (Python, Tcl, Perl).
Synopsys PrimeTime, Cadence Tempus, Synopsys Design Compiler, Cadence Genus, Xilinx Vivado, Synopsys Fusion Compiler, Formality (Cadence LEC), TCM, Fishtail, Python, Tcl, Perl, Unix shell, C Shell
4d
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SoC Static Timing Analysis (STA) Engineer, HBM
Folsom or Richardson
$199k-$347k/yr OnsiteFull Time
15+ YOE15+ years chip-level STA ownership at advanced nodes (5nm+), expertise with Synopsys PrimeTime or Cadence Tempus, deep timing methodology knowledge, and Python/Tcl scripting for automation.
Synopsys PrimeTime, Cadence Tempus, Python, Tcl
4d
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SoC Static Timing Analysis (STA) Engineer, HBM
Folsom or Richardson
$199k-$347k/yr OnsiteFull Time
15+ YOE15+ years chip-level STA and sign-off experience at advanced nodes, expertise with Synopsys PrimeTime/Cadence Tempus, deep timing methodology knowledge, and Python/Tcl scripting for flow automation.
Synopsys PrimeTime, Cadence Tempus, Python, Tcl, Synopsys Design Constraints (SDC)
1mo
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Signoff Static Timing Analysis and Spice CAD Engineer
San Diego, California, United States
$140k-$210k/yr OnsiteFull Time
4+ YOEEngineering degree (BS/MS/PhD) plus multi-year ASIC/STA experience; deep STA and SPICE knowledge, signoff timing and cell characterization experience, CAD development skills, Python and TCL scripting proficiency, strong communication and problem-solving.
Python, TCL, STA, SPICE, EDA
2mo
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SOC Physical Design Static Timing Analysis Engineer
Phoenix or Santa Clara
$164k-$312k/yr HybridFull Time
7+ YOEBachelor's/Master's/PhD in EE/CE/CS; 7+ yrs SOC timing analysis; 3+ yrs tools; TCL scripting; timing constraints; clock network; PVT; cross-team collaboration.
Timing Analysis Tools, Extraction Tools, Physical Design Tools, TCL Scripting
3mo
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CPU Design Timing Engineer
Santa Clara or North America
OnsiteFull Time
3+ YOEBS degree and 3+ years; static timing analysis, noise analysis, variation modeling; TCL and Python or Perl.
PrimeTime, Tempus, TCL, Python, Perl
2mo
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Senior Static Timing Analysis (STA) Methodology Engineer
Saratoga, California, United States
$120k-$220k/yr OnsiteFull Time
8+ YOESenior STA/Timing methodology engineer with 8+ years in STA, scripting (Tcl/Python/Perl), signoff; BS/MS in ECE or related; onsite in Saratoga, CA.
PrimeTime, PT-SI, PT-PX, PT-ECO, Tcl, Python, Perl
2mo
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Design Automation Engineer
San Jose, California, United States
$143k-$215k/yr OnsiteFull Time
8+ YOE8+ years in Static Timing Analysis, Liberty models, STA flow development, and scripting (Python, Perl, Tcl, Shell).
Synopsys PrimeTime, Cadence Tempus, Python, Tcl, Shell, Perl, Fusion Compiler, Innovus, Cadence Pegasus
3w
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Senior Physical Design and Timing Engineer
Santa Clara or Austin or Hillsboro or Durham
$136k-$265k/yr HybridFull Time
3+ YOEBS in Electrical or Computer Engineering with 5+ years or MS with 3+ years; strong static timing analysis, synthesis, physical design, timing convergence, RTL/logic understanding; proficiency with Perl, Tcl, Make, Python.
Perl, Tcl, Make, Python
1mo
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Sr. Staff Engineer, Timing Methodology & Signoff
Austin or Hsinchu or Shanghai or Shenzhen or Singapore
OnsiteFull Time
8+ YOE8+ years in timing analysis and convergence; expertise with static timing analysis and SoC signoff; experience with Synopsys Primetime or Cadence Tempus; proficiency in TCL or Python; strong cross-functional collaboration and problem solving.
Synopsys Primetime, Cadence Tempus, Synopsys, Cadence, TCL, Python, Fusion Compiler, Innovus
1w
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Physical Design Lead, Static Timing Analysis
Sunnyvale, California, United States
$192k-$279k/yr OnsiteFull Time
10+ YOE5+ MgmtBachelor's in EE/CE/CS or equivalent,10+ years STA experience with 5+ years technical leadership, experience with full-chip timing convergence, timing constraint authoring, Tcl and EDA tool usage, and cross-chip clock analysis.
Synopsys Design Constraints (SDC), Tcl, PrimeTime, Tempus, Timevision, STAR-RC, SPICE
1mo
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Physical Design Engineer - Static Timing Analysis, Annapurna Labs, Cloud Scale Machine Learning
Cupertino or Austin
$136k-$213k/yr OnsiteFull Time
1+ YOEDegree in EE/CS with relevant experience (BS+6 / MS+4 / PhD+2), 1+ years STA and timing constraint development, scripting (Tcl/Perl/Python), timing analysis fundamentals, familiarity with PrimeTime/Tempus and RTL-to-GDSII physical design flow.
PrimeTime, Tempus, PT-DMSA, Tempus-ECO, Tweaker, STAR-RC, Quantus, SPICE, SPECTRE, Tcl, Perl, Python
4d
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ASIC Physical Design and Timing Engineer - New College Grad 2026
Santa Clara, California, United States
$116k-$219k/yr OnsiteFull Time
Master's degree or equivalent experience in ECE, proficiency in static timing analysis (STA), timing convergence, timing constraints, and industry EDA tools; strong communication and problem-solving skills.
Static Timing Analysis (STA), EDA, AI tools
2mo
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Physical Design Engineer
Austin or Boulder or Chicago or London or New York City or Seattle
$200k-$300k/yr OnsiteFull Time
Experience in high-performance ASIC design; digital logic; DFT concepts; scripting (Python, Tcl, shell); static timing analysis; timing closure; Innovus/PrimeTime.
Innovus, PrimeTime, Python, Tcl, shell
1mo
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Sr Principal Application Engineer
San Jose, California, United States
$123k-$229k/yr OnsiteFull Time
12+ YOEMS in CS/CE/EE plus 12+ years experience; strong digital design, static timing analysis, RTL-to-GDSII implementation; scripting in Perl/Tcl/Python; experience with synthesis, place-and-route, timing and power closure.
Tcl, Perl, Python, Genus, Innovus, Conformal, Tempus, Modus, Voltus
1mo
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Lead, Firmware Engineer
Newark, California, United States
HybridFull Time
10+ YOE3+ Mgmt10+ years firmware/embedded experience with 3+ years leading firmware teams; shipping embedded software for electromechanical products; expertise in real-time systems, drivers, BSP, code review, CI/CD, static analysis, and test automation.
1w
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Senior FPGA Design Engineer (Nextest, Tualatin, OR)
Tualatin or San Jose
$170k-$273k/yr OnsiteFull Time
8+ YOEB.S. or M.S. in electrical engineering,8+ years relevant experience,RTL/Verilog,Intel/Xilinx tool flows,static timing analysis,FPGA transceivers,EM simulation lab validation,C/C++,Linux/Windows proficiency.
C, C++, Verilog HDL, Intel/Xilinx FPGA tool flows, UVM, Linux, Windows, oscilloscope, power supply, waveform generator, ATE
2w
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Software Engineer (Active Secret Clearance Required)
Rancho Bernardo, California, United States
$92k-$138k/yr OnsiteFull Time
2+ YOESTEM degree, 2+ years software engineering experience (or MS/PhD with 0 years), familiarity with safety-critical embedded real-time software, SDLC/Agile, C/C++, Python and scripting, RTOS experience, static/dynamic analysis tools, and an active U.S. Secret clearance.
C, C++, Python, PowerShell, VBScript, Bash, KornShell, VxWorks, Integrity, Real Time Embedded Linux, Coverity, Fortify, SonarQube, Atlassian, Jira, GitHub, GitLab, Jenkins, DOORs, Rhapsody, Cameo, MATLAB, JavaScript, TCP/IP, UDP, SNMP
3w
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ASIC Engineer, Physical Design
Sunnyvale or Austin
$178k-$250k/yr OnsiteFull Time
8+ YOEBachelor's degree (or equivalent) and 8+ years in ASIC physical design with end-to-end implementation, experience with industry EDA tools, static timing analysis and multi-corner closure at advanced nodes (7nm or below); scripting and low-power experience preferred.
Synopsys IC Compiler, Cadence Innovus, Primetime, Calibre, Python, Tcl
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