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Senior Physical Design and Timing Engineer
Santa Clara or Austin or Hillsboro or Durham
$136k-$265k/yr HybridFull Time
3+ YOEBS in Electrical or Computer Engineering with 5+ years or MS with 3+ years; strong static timing analysis, synthesis, physical design, timing convergence, RTL/logic understanding; proficiency with Perl, Tcl, Make, Python.
Perl, Tcl, Make, Python
1mo
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Sr. Staff Engineer, Timing Methodology & Signoff
Austin or Hsinchu or Shanghai or Shenzhen or Singapore
OnsiteFull Time
8+ YOE8+ years in timing analysis and convergence; expertise with static timing analysis and SoC signoff; experience with Synopsys Primetime or Cadence Tempus; proficiency in TCL or Python; strong cross-functional collaboration and problem solving.
Synopsys Primetime, Cadence Tempus, Synopsys, Cadence, TCL, Python, Fusion Compiler, Innovus
1mo
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Physical Design Engineer - Static Timing Analysis, Annapurna Labs, Cloud Scale Machine Learning
Cupertino or Austin
$136k-$213k/yr OnsiteFull Time
1+ YOEDegree in EE/CS with relevant experience (BS+6 / MS+4 / PhD+2), 1+ years STA and timing constraint development, scripting (Tcl/Perl/Python), timing analysis fundamentals, familiarity with PrimeTime/Tempus and RTL-to-GDSII physical design flow.
PrimeTime, Tempus, PT-DMSA, Tempus-ECO, Tweaker, STAR-RC, Quantus, SPICE, SPECTRE, Tcl, Perl, Python
3mo
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CAD Engineer - Timing for Gate-Level Flows & Methodologies
Austin or San Jose
HybridFull Time
10+ YOEBS in a related field and 10+ years of experience; strong static timing analysis, CAD flows, and scripting in Python/Tcl; experience with EDA tools and SoC timing.
Python, Tcl, Static Timing Analysis, EDA tools, gate-level CAD flows
3mo
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CAD Engineer - Timing for Gate-Level Flows & Methodologies
Austin or San Jose
OnsiteFull Time
3+ YOEBS with 3 years of relevant industry experience; experience with static timing analysis tools; programming in Python/Tcl; STA of large high-performance SoCs; knowledge of timing constraints and margins; strong communication.
Static Timing Analysis, Python, Tcl, EDA tools
3mo
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Physical Design Engineer
Austin or Boulder or Chicago or London or New York City or Seattle
$200k-$300k/yr OnsiteFull Time
Experience in high-performance ASIC design; digital logic; DFT concepts; scripting (Python, Tcl, shell); static timing analysis; timing closure; Innovus/PrimeTime.
Innovus, PrimeTime, Python, Tcl, shell
1mo
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CPU SRAM Design Engineer
Austin, Texas, United States
$123k-$184k/yr OnsiteFull Time
2+ YOEBachelor's in EE/CE/CS (or higher) with relevant hardware engineering experience; experience designing SRAM/register files, custom design flows, circuit simulation, Monte Carlo and static timing analysis, and memory layout/verification.
NanoTime, Ansys EMIR analysis, ESP-CV, Liberate power analysis, Verilog
4w
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ASIC Engineer, Physical Design
Sunnyvale or Austin
$178k-$250k/yr OnsiteFull Time
8+ YOEBachelor's degree (or equivalent) and 8+ years in ASIC physical design with end-to-end implementation, experience with industry EDA tools, static timing analysis and multi-corner closure at advanced nodes (7nm or below); scripting and low-power experience preferred.
Synopsys IC Compiler, Cadence Innovus, Primetime, Calibre, Python, Tcl
1mo
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CPU SRAM Design Engineer - Sr Staff / Principal
Austin, Texas, United States
$179k-$268k/yr OnsiteFull Time
12+ YOEBachelor's in EE with 12+ yrs (or MS/PhD with equivalent experience); experience designing SRAM, custom design flows, circuit simulation/Monte Carlo, and static timing analysis. Familiarity with NanoTime, Ansys EMIR, ESP-CV, Liberate, Verilog, BIST/DFT.
NanoTime, Ansys EMIR, ESP-CV, Liberate, Verilog
1mo
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Senior CPU RTL Design Engineer – Power Management
Austin or Phoenix
$164k-$269k/yr HybridFull Time
7+ YOEBachelor's (9+ years) or Master's (7+ years) in ECE/CE/CS. Experience in low-power CPU/SoC RTL design, power management (DVFS, power states), RTL development (Verilog/SystemVerilog), debug and system-level design. Preferred: CDC, static timing analysis, UPF, lint.
SystemVerilog, Verilog, x86 assembly, CDC, UPF, static timing analysis, lint
2w
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Director, Silicon Design Engineering
Santa Clara or Austin or Hillsboro
$221k-$312k/yr HybridFull Time
12+ YOERequires 6–12+ years timing/physical design experience, BS in EE/CE (or equivalent), proficiency in static timing analysis, timing constraint generation, SoC clocking, TCL scripting, and collaboration with cross-functional teams.
TCL, TFM, EDA tools
2mo
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Chip Lead / Physical Design Director
Austin, Texas, United States
OnsiteFull Time
15+ YOEFifteen+ years in Physical Design; BS in CS/Engineering; strong Digital Design, Semiconductor fundamentals, and Static Timing Analysis; IC backend flows and EDA tools; complete design closure; 7nm+ nodes; scripting in Tcl/Perl/Python; strong customer-facing skills.
Genus, Innovus, Conformal, Tempus, Modus, Voltus, ICC, ICC2, DC, Primetime, Scripting (Tcl, Perl, Python)