2 static timing analysis engineer jobs at 2 companies in Colorado
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ASIC Physical Design Engineer
Boulder or Beaverton or Louisville
HybridFull Time
RalliantNew York Stock Exchange: RAL: Sells precision instruments and sensors for diverse industrial sectors.
5+ YOEBS in Electrical Engineering, 5+ years ASIC physical design experience from RTL to GDS, proficiency with Cadence/Synopsys/Siemens EDA, static timing analysis, signoff checks, and scripting (Tcl, Python, Perl, shell).
Cadence Design SystemsNASDAQ: CDNS: Develops computational software and hardware for electronic system design.
10+ YOE10+ years physical design experience; BS in CS/CE/EE required (MS preferred); strong digital design and static timing analysis knowledge; scripting with Tcl/Perl/Python; experience with advanced nodes and backend EDA flows; strong customer communication skills.