3 static timing analysis engineer jobs at 1 company in Frisco, TX
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SoC Static Timing Analysis (STA) Engineer, HBM
Folsom or Richardson
$199k-$347k/yr OnsiteFull Time
15+ YOE15+ years chip-level STA ownership at advanced nodes (5nm+), expertise with Synopsys PrimeTime or Cadence Tempus, deep timing methodology knowledge, and Python/Tcl scripting for automation.
Synopsys PrimeTime, Cadence Tempus, Python, Tcl
3w
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SoC Static Timing Analysis (STA) Engineer, HBM
Folsom or Richardson
$199k-$347k/yr OnsiteFull Time
15+ YOE15+ years chip-level STA and sign-off experience at advanced nodes, expertise with Synopsys PrimeTime/Cadence Tempus, deep timing methodology knowledge, and Python/Tcl scripting for flow automation.
Synopsys PrimeTime, Cadence Tempus, Python, Tcl, Synopsys Design Constraints (SDC)
3mo
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Senior SOC Physical Design Engineer, HBM
Richardson, Texas, United States
OnsiteFull Time
3+ YOEHands-on SoC physical implementation experience using EDA tools (Innovus, Fusion Compiler, Calibre, ICV, PrimeTime/Tempus); knowledge of SDC, UPF/CPF, static timing analysis, signoff flows; 3+ years physical design or SoC implementation experience; Tcl/Python scripting preferred.
Innovus, Fusion Compiler, IC Validator (ICV), Calibre, PrimeTime, Tempus, Synopsys Design Constraints (SDC), Unified Power Format (UPF), Common Power Format (CPF), Ansys, Tcl, Python