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SoC Static Timing Analysis (STA) Engineer, HBM
Folsom or Richardson
$199k-$347k/yr OnsiteFull Time
15+ YOE15+ years chip-level STA ownership at advanced nodes (5nm+), expertise with Synopsys PrimeTime or Cadence Tempus, deep timing methodology knowledge, and Python/Tcl scripting for automation.
Synopsys PrimeTime, Cadence Tempus, Python, Tcl
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SoC Static Timing Analysis (STA) Engineer, HBM
Folsom or Richardson
$199k-$347k/yr OnsiteFull Time
15+ YOE15+ years chip-level STA and sign-off experience at advanced nodes, expertise with Synopsys PrimeTime/Cadence Tempus, deep timing methodology knowledge, and Python/Tcl scripting for flow automation.
Synopsys PrimeTime, Cadence Tempus, Python, Tcl, Synopsys Design Constraints (SDC)
2mo
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SoC Timing (Static Timing Analysis/STA) Engineer, HBM
Richardson, Texas, United States
OnsiteFull Time
10+ YOE10+ years of hands-on chip-level static timing analysis and sign-off; expertise with Synopsys PrimeTime and Cadence Tempus; MMMC, OCV/AOCV, SI; Python/Tcl scripting for automation; experience with HBM/DRAM and die-to-die interfaces.
Synopsys PrimeTime, Cadence Tempus, Python, Tcl
2mo
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SoC Timing (Static Timing Analysis/STA) Engineer, HBM
Richardson, Texas, United States
OnsiteFull Time
10+ YOE10+ years chip-level static timing analysis experience at advanced nodes, expertise with Synopsys PrimeTime/Cadence Tempus, SDC constraint development, Python/Tcl scripting, and advanced timing methodologies.
Synopsys PrimeTime, Cadence Tempus, Synopsys Design Constraints (SDC), Python, Tcl, Liberty timing models
2mo
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SOC Timing Analysis (STA) Engineer ,HBM
Richardson, Texas, United States
OnsiteFull Time
10+ YOE10+ years in chip-level static timing analysis with full sign-off ownership; experience with SDC, MMMC, and tool flows (PrimeTime, Tempus); collaboration with RTL/PD/DFT and scripting for automation.
Synopsys PrimeTime, Cadence Tempus, Python, Tcl, SDC, JTAG, MBIST, DFT, clock tree synthesis, routing, synthesis
2mo
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SOC Timing Analysis (STA) Engineer ,HBM
Richardson, Texas, United States
OnsiteFull Time
10+ YOE10+ years chip-level static timing analysis experience with Synopsys PrimeTime or Cadence Tempus, SDC development, Python/Tcl automation, RTL-to-GDS flow knowledge, and full sign-off ownership at advanced nodes.
Synopsys PrimeTime, Cadence Tempus, Synopsys Design Constraints (SDC), Python, Tcl, GDS
2mo
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DMTS Digital Design Engineer / Chip Lead
Minneapolis or Boise or Folsom or Richardson or San Jose
$206k-$410k/yr OnsiteFull Time
10+ YOE10+ years ASIC/digital design experience with prior tape-out; BS/MS/PhD in EE/CE or related; expert SystemVerilog; synthesis (Design Compiler/Genus), static timing analysis (PrimeTime/Tempus), RTL simulation (VCS/Xcelium), CDC tools; chip architecture and IP integration experience.
SystemVerilog, Synopsys Design Compiler, Cadence Genus, PrimeTime, Tempus, VCS, Xcelium, Verdi, DVE, SpyGlass, JasperGold
2mo
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Senior SOC Physical Design Engineer, HBM
Richardson, Texas, United States
OnsiteFull Time
3+ YOEHands-on SoC physical implementation experience using EDA tools (Innovus, Fusion Compiler, Calibre, ICV, PrimeTime/Tempus); knowledge of SDC, UPF/CPF, static timing analysis, signoff flows; 3+ years physical design or SoC implementation experience; Tcl/Python scripting preferred.
Innovus, Fusion Compiler, IC Validator (ICV), Calibre, PrimeTime, Tempus, Synopsys Design Constraints (SDC), Unified Power Format (UPF), Common Power Format (CPF), Ansys, Tcl, Python