12 uvm jobs at 4 companies in Washington, DC
1w
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FPGA Verification Engineer, Bespoke Solutions
Jessup or Arlington or Herndon
$136k-$184k/yr OnsiteFull Time
4+ YOERequires US citizenship and active TS/SCI clearance; Bachelor's in electrical/communications engineering; 3+ years design and 4+ years verification experience with SystemVerilog/UVM; FPGA/ASIC verification experience.
SystemVerilog, UVM, Xilinx Vivado, AMD Vivado, Synopsys VCS, Cadence Xcelium, SystemVerilog Assertions (SVA)
4w
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ASIC/FPGA Verification Engineer (Experienced, Lead, or Senior)
El Segundo or Huntington Beach or Fairfax
$120k-$239k/yr OnsiteFull Time
5+ YOEBachelor's in engineering or related field, 5+ years ASIC/FPGA verification experience, proficiency in SystemVerilog/UVM, OOP principles, coverage and code-coverage closure, waveform debug, revision control, and Linux.
UVM, SystemVerilog, SystemVerilog Assertions, svn, cvs, git, Linux, Palladium, Make, Perl, Python
2mo
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Engineer Principal - FPGA Design - $10K Sign On Bonus
Chantilly, Virginia, United States
$118k-$201k/yr HybridFull Time
6+ YOEBachelor's in engineering plus 6+ years experience (or equivalent). Must be U.S. person, eligible for Top Secret/SCI. Strong FPGA experience with VHDL/Verilog/SystemVerilog, Xilinx Vivado/Vitis, ModelSim/QuestaSim, OVM/UVM, high-speed digital design and SoC architectures.
VHDL, Verilog, SystemVerilog, Xilinx Vivado, Xilinx Vitis, Mentor ModelSim, QuestaSim, OVM, UVM, Mentor HyperLynx
4w
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ASIC/FPGA Verification Engineer (Experienced, Lead, or Senior)
El Segundo or Huntington Beach or Fairfax
$120k-$239k/yr OnsiteFull Time
5+ YOEBachelor's degree in engineering or related field, 5+ years ASIC/FPGA verification experience, proficiency with SystemVerilog/UVM, SV Assertions, revision control (svn/cvs/git), Linux, and waveform/debug tools; ability to obtain U.S. Secret clearance (U.S. citizenship required).
UVM, SystemVerilog, SystemVerilog Assertions, svn, cvs, git, Linux, Palladium, Make, Perl, Python, ARM, JESD204C, PCIe, Ethernet
1mo
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Senior FPGA Engineer
Fairfax, Virginia, United States
$76k-$141k/yr OnsiteFull Time
4+ YOEBachelor's in EE/CE (or MS) and 6+ years (4+ with MS) experience in FPGA RTL design, timing closure, simulation/verification, Vivado/VHDL/SystemVerilog experience, lab bring‑up, and high‑speed interface integration.
Xilinx, Zynq Ultrascale+ MPSoC, Zynq Ultrascale+ RFSoC, Versal ACAP, Versal AI Engines, Vivado Design Suite, Vivado IP Integrator, Vivado HW Debugger, Chipscope, SmartDebug, Libero, Git, Modelsim, Questasim, Aldec, UVVM, UVM, OVM, VHDL, SystemVerilog, MATLAB, Simulink, Linux, C, C++
2mo
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Senior Principal II Engineer – FPGA Design - $20K Sign On Bonus
Chantilly, Virginia, United States
$150k-$254k/yr HybridFull Time
10+ YOEBachelor's in engineering plus 10+ years' related experience; expertise in FPGA/SoC design, VHDL/Verilog/SystemVerilog, Xilinx Vivado/Vitis, ModelSim/QuestaSim; eligible for Top Secret/SCI clearance; strong communication and leadership.
VHDL, Verilog, SystemVerilog, Xilinx Vivado, Vitis, ModelSim, QuestaSim, OVM, UVM, Mentor Graphics HyperLynx
2mo
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Engineer Principal - FPGA Design - $20K Sign On Bonus
Chantilly, Virginia, United States
$118k-$201k/yr HybridFull Time
6+ YOEBachelor's degree in engineering plus 6+ years related experience; active Top Secret/SCI clearance required; expertise in FPGA design (VHDL/Verilog/SystemVerilog), Xilinx Vivado/Vitis, ModelSim/QuestaSim; strong communication and technical leadership skills.
VHDL, Verilog, SystemVerilog, Xilinx Vivado, Vitis, Mentor ModelSim, QuestaSim, OVM, UVM, HyperLynx, PCIe, Ethernet
2mo
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Engineer Senior Principal - FPGA Design - $20K Sign On Bonus
Chantilly, Virginia, United States
$133k-$226k/yr HybridFull Time
8+ YOEBachelor's in Engineering +8 years (or equivalent); active Top Secret/SCI clearance; experience with VHDL/Verilog/System Verilog, Xilinx Vivado/Vitis, Mentor ModelSim/QuestaSim, FPGA SoC design, and high-speed digital systems.
VHDL, Verilog, System Verilog, Xilinx Vivado, Xilinx Vitis, Mentor ModelSim, Mentor QuestaSim, OVM, UVM, Mentor Graphics HyperLynx
2mo
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Senior Principal II Engineer – FPGA Design - $40K Sign On Bonus
Chantilly, Virginia, United States
$150k-$254k/yr HybridFull Time
10+ YOEBachelor's in engineering +10 years (or equivalent), active TS/SCI clearance, expertise in VHDL/Verilog/System Verilog, Xilinx Vivado/Vitis, Mentor Modelsim/Questasim, and FPGA SoC design.
VHDL, Verilog, System Verilog, Xilinx Vivado, Vitis, Mentor Modelsim, Questasim, OVM, UVM, Hyperlynx
2mo
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Engineer Senior Principal - FPGA Design - $10K Sign On Bonus
Chantilly, Virginia, United States
$133k-$226k/yr HybridFull Time
8+ YOEBachelor's in engineering +8 yrs experience, VHDL/Verilog/System Verilog, Xilinx Vivado/Vitis, ModelSim/QuestaSim, ability to obtain Top Secret/SCI clearance, FPGA SoC design and technical leadership experience.
VHDL, Verilog, System Verilog, Xilinx Vivado, Vitis, Mentor ModelSim, QuestaSim, OVM, UVM, Mentor Graphic Hyperlynx
1mo
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Associate ASIC/FPGA Design or Verification Engineer
El Segundo or Huntington Beach or Fairfax
$99k-$133k/yr OnsiteFull Time
2+ YOEUS citizenship and ability to obtain U.S. Secret clearance; BS in engineering or related field; experience with ASIC/FPGA design or verification and HDL (Verilog/VHDL/System Verilog); familiarity with verification methodologies and scripting.
Verilog, VHDL, System Verilog, System Verilog Assertions, UVM, Palladium, Make, Perl, Python, svn, cvs, git, Linux, JESD204C, PCIe, Ethernet
1mo
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Associate ASIC/FPGA Design or Verification Engineer
El Segundo or Huntington Beach or Fairfax
$99k-$133k/yr OnsiteFull Time
2+ YOEUS citizenship with ability to obtain U.S. Secret clearance, Bachelor\u0000s degree in a relevant field, experience with ASIC/FPGA design or verification, and RTL experience with Verilog/VHDL/SystemVerilog.
Verilog, VHDL, SystemVerilog, System Verilog Assertions, UVM, Palladium, Make, Perl, Python, svn, cvs, git, Linux, ARM, JESD204C, PCIe, Ethernet