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SoC Verification Engineer – NoC / UVM
San Jose, California, United States
$146k-$250k/yr HybridFull Time
Expertise in SystemVerilog and UVM, ASIC/SoC verification, constraint-random and coverage-driven methodologies, formal verification (SVA); experience with Synopsys VCS and Cadence IES preferred; B.S. or M.S. in computer/electrical engineering.
SystemVerilog, UVM, OVM, VMM, Verilog, SystemVerilog Assertions (SVA), Synopsys VCS, Cadence IES, Cadence IEV, Jasper, Synopsys VC-Formal, Magellan
2mo
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Principal Firmware Verification Engineer - UVM (Onsite)
Marlborough, Massachusetts, United States
$108k-$205k/yr OnsiteFull Time
8+ YOEDegree in STEM with 8+ years experience or advanced degree with 5+ years; 4+ years UVM; SystemVerilog and VHDL; experience with FPGA/SoC/CPLD verification; familiar with AXI/ SPI/ I2C/ PCIe/ UART/ Gb Ethernet; scripting in TCL/Perl/Python; Git/SVN; cross-functional Agile.
UVM, SystemVerilog, VHDL, AXI, SPI, I2C, PCIe, UART, Gb Ethernet, TCL, Perl, Python, Git, SVN
2w
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Non-Union - Foreperson (UVM)
Prescott or Prescott Valley or Sedona or Cottonwood or Dewey or Chino Valley
FieldFull Time
1+ YOELead a field crew in utility vegetation management; minimum 12 months vegetation management experience; high school diploma; valid driver's license required (CDL preferred); CPR and First Aid; DOT medical certificate where applicable; complete required field trainings and pass Foreperson assessment.
2mo
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UVM Full Stack Developer 1 (Kent, OH, US, 44240)
Kent, Ohio, United States
OnsiteFull Time
1+ YOEBachelor’s degree in CS/IT or equivalent; strong Python/Java/Node.js (PHP also ok); REST APIs; databases; testing; good communication; office-based work.
Python, Java, Ruby, Node.js, PHP, Express, Nginx, MySQL, PostgreSQL, MongoDB, Redis, Docker, AWS, GCP, Azure, React, Angular, Vue.js, Jest, Cypress, Git, GIS
3d
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Senior ASIC Engineer
Santa Clara, California, United States
$127k-$190k/yr OnsiteFull Time
2+ YOE2+ years ASIC verification experience, UVM experience, ability to build UVM testbenches, knowledge of digital logic, SoC architecture, AMBA protocols, scripting, and verification strategy.
UVM, ARM, AMBA, AHB, AXI
2w
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Integrated Circuit Design Verification Engineer
Vancouver, Washington, United States
$173k-$259k/yr OnsiteFull Time
10+ YOE10+ years ASIC design verification experience; strong UVM/SystemVerilog skills; Siemens Questa; develop UVM/assertion testbenches, functional and code coverage, scripting/automation in Linux.
UVM, SystemVerilog, Siemens Questa, TCL, Make, Perl, Python, Shell, Linux
1mo
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ASIC Design Verification Technical Lead, TPU
Sunnyvale, California, United States
$192k-$278k/yr OnsiteFull Time
10+ YOE10+ years verif. experience with UVM/SystemVerilog; lead verification and testbench development.
SystemVerilog, UVM, Python, Perl, Shell, Bash, Linux
1mo
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AMS Verification Engineer (Senior/Staff/Senior Staff/Principal)
United Kingdom or Armenia or Italy or United States or Estonia or India
RemoteFull Time
10+ YOEM.S. or Ph.D. in EE, 10+ years AMS/mixed-signal or high-speed interface verification, hands-on SystemVerilog/UVM/UVM-AMS and Verilog-AMS/RNM/wreal experience, SerDes expertise, and scripting with Python/Perl/Tcl.
SystemVerilog, UVM, UVM-AMS, Verilog-AMS, RNM, wreal, Cadence Xcelium AMS, Synopsys VCS AMS, Siemens Questa ADMS, Python, Perl, Tcl, MATLAB
1mo
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Design Verification Engineer - Viasat Government
Marlborough or Carlsbad
$133k-$210k/yr OnsiteFull Time
5+ YOEBachelor's in Electrical or Computer Engineering; 5+ years hardware verification with SystemVerilog/UVM; RTL verification; strong SystemVerilog/UVM; experience with industry EDA tools; US citizenship and active Secret clearance; willingness to travel up to 10%
SystemVerilog, UVM, Siemens Questa, Cadence, Synopsys, Mentor, Python, TCL
3mo
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MLA Design Verification Engineer, Annapurna Labs
Austin or Cupertino
$136k-$213k/yr OnsiteFull Time
3+ YOE3+ years design verification with SystemVerilog/UVM; testbench development; Bachelors in Electrical Engineering
SystemVerilog, UVM, C, C++
3mo
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Senior Design Verification Engineer
Austin or Chandler or Greensboro
HybridFull Time
5+ YOEExperience in silicon design/ASIC verification; HDL/SystemVerilog/UVM; cross-disciplinary collaboration.
Verilog, VHDL, SystemVerilog, UVM
2mo
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SMTS Design Verification Engineer
Minneapolis or Boise or Folsom or Richardson or San Jose
$178k-$389k/yr OnsiteFull Time
6+ YOEBS/MS/PhD in EE/CE or related; 6+ years UVM/SystemVerilog functional verification; experience building UVM testbenches, coverage-driven methodology, protocol/interface verification, RTL/testbench debug, and post-silicon bring-up support.
UVM, SystemVerilog, SystemVerilog Assertions (SVA), JasperGold, VC Formal, Verilog-AMS, Real-number modeling (RNM), ATE
2mo
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Principal Design Verification Engineer
Austin or Santa Clara
$153k-$290k/yr OnsiteFull Time
8+ YOE8+ years in design verification of CPU/SoC, SystemVerilog/UVM, constrained random verification, and scripting.
SystemVerilog, UVM, Python, Perl, Shell
3mo
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Design Verification Engineer
Cupertino or Santa Clara or Sunnyvale
OnsiteFull Time
3+ YOEBS + 3 years experience in digital verification; SystemVerilog, Python/Perl, UVM, architecture knowledge.
SystemVerilog, Python, Perl, C, C++, Assembly, UVM, Digital verification tools
2mo
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Senior ASIC Design Verification Engineer
Minneapolis, Minnesota, United States
OnsiteFull Time
3+ YOE3+ years IP/SoC verification; UVM; SystemVerilog; Python; strong debugging and communication skills.
SystemVerilog, Python, UVM, Constrained-Random Verification, Python-based testbenches
2mo
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Staff DV Engineer
Saratoga, California, United States
$120k-$220k/yr OnsiteFull Time
6+ YOE6+ years design verification in semiconductor; Verilog/SystemVerilog; UVM; C/C++; Python; leadership experience.
Verilog, SystemVerilog, UVM, C, C++, Python, VHDL
3mo
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Technical Lead, Design Verification
Santa Clara, California, United States
$159k-$238k/yr OnsiteFull Time
Lead verification for SoCs, develop UVM environments, mentor engineers, strong SystemVerilog, Python, ARM/NoC expertise.
SystemVerilog, UVM, Python, Xcelium, Questa, VCS
3mo
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Principal Digital Verification Engineer
Duluth, Georgia, United States
HybridFull Time
8+ YOEMasters or Bachelors in Electrical/Computer Engineering with 8+ or 10+ years of experience; DDR5 verification experience; UVM methodology
UVM, SystemVerilog, DDR5
2mo
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R&D Engineer IC Design
San Jose, California, United States
$120k-$192k/yr OnsiteFull Time
6+ YOE6+ years in design verification; master’s in ECE/CS; SystemVerilog, scripting; UVM preferred; knowledge of networking and switching.
SystemVerilog, UVM, Scripting, Testbenches, ATE testing
2mo
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Design Verification (DV) Engineer
Austin or Boulder or Chicago or London or New York City
$175k-$250k/yr OnsiteFull Time
2+ YOE2+ years RTL verification for FPGA/ASIC; SystemVerilog/UVM; Python; Linux; Verilator; Cocotb; C++ is a plus.
SystemVerilog, UVM, Python, Verilator, Cocotb, Linux, C++
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