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ASIC Verification Engineer
Santa Clara, California, United States
$116k-$190k/yr HybridFull Time
2+ YOEBS or MS in EE/CS/CE; 2+ years verification; strong verification methodology experience; C++ and/or SystemVerilog; UVM; tools: VCS, Debussy, GDB; strong communication.
C++, SystemVerilog, VCS, Debussy, GDB, UVM, verification methodologies
2mo
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Director, Design Verification
San Jose, California, United States
$219k-$351k/yr OnsiteFull Time
15+ YOEBE/MS in Computer/Electrical Engineering or Computer Science; 15+ years ASIC verification; leadership in verification; multiple tape-outs; UVM, C++, SystemVerilog; strong communication and collaborative skills.
UVM, C++, SystemVerilog, verification tools
2mo
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Principal SoC Verification
San Diego, California, United States
$184k-$273k/yr OnsiteFull Time
10+ YOEBS/ MS/ PhD in Computer Engineering, Electrical Engineering, or Computer Science with 5-15+ years in verification and firmware/software; strong UVM/SystemVerilog/C/C++/DPI; test bench development; teamwork and problem solving.
UVM, SystemVerilog, C, C++, DPI, Verification
2mo
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Verification Engineer
San Jose or Fort Collins
$120k-$192k/yr OnsiteFull Time
8+ YOEBS in Electrical/Electronic Eng or CS; 8+ years ASIC/RTL verification; SystemVerilog/UVM/OVM; Python/C++; block- and system-level verification; strong debugging and collaboration.
SystemVerilog, UVM, OVM, Python, C/C++, RTL
2w
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Verification Engineer
San Jose, California, United States
OnsiteFull Time
3+ YOEBS/MS in ECE (or equivalent), 3+ years ASIC/SoC functional verification, strong UVM/SystemVerilog skills, testbench development, scripting in Python/Perl/TCL, and familiarity with regression/CI and hardware-assisted verification.
UVM, SystemVerilog, Python, Perl, TCL, Verilog-AMS, Palladium, Veloce, HAPS, Protium, UPF, UCIe, PCIe, CXL, Ethernet, UALink, VIP
3mo
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Verification Specialist
United States
OnsiteFull Time
1+ YOE1-2 years benefits verification; knowledge of medical billing; HIPAA; high school diploma; EMR proficiency.
EMR system, MS Office, Windows
2w
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Verification Engineer
San Jose or San Diego or Austin or Longmont
$124k-$213k/yr HybridFull Time
Experience in IP/ASIC/FPGA verification using UVM, Verilog/SystemVerilog, scripting (Python/Perl), and developing test plans and regression suites; bachelor’s or master’s in computer or electrical engineering.
UVM, Verilog, System Verilog, Python, Perl, PCIe, CXL, NVMe, Ethernet, HLS
3d
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Verification Engineer
Ball Ground, Georgia, United States
$80k-$100k/yr OnsiteFull Time
2+ YOE2+ years in medical device design verification or related field; proficiency with V-model, requirements traceability matrix, formal protocol writing; knowledge of IEC 60601-1 and IEC 62304; statistical sample size and test data analysis.
1mo
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Verification Engineer Senior
Austin, Texas, United States
$191k-$269k/yr HybridFull Time
6+ YOEBachelor's in EE/CE/CS + 8+ yrs or Master's + 6+ yrs in ASIC/FPGA verification; SystemVerilog/UVM, OOP, coverage-driven verification, constrained-random testing, protocol experience (AXI, CHI, UART, SPI, I2C/I3C), strong debug skills.
SystemVerilog, UVM, Synopsys VCS, Cadence Xcelium
3w
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Staff Verification Engineer
Pittsburgh, Pennsylvania, United States
$120k-$200k/yr OnsiteFull Time
5+ YOE5+ years ASIC/SoC verification experience, Bachelor’s or Master’s in electrical/computer engineering, expertise in SystemVerilog/UVM, constrained-random and assertion verification, scripting in Python/Perl/Tcl/shell, Cadence/Mentor/Synopsys tool experience, protocol knowledge (Ethernet, PCIe, CXL, AMBA).
SystemVerilog, UVM, Python, Perl, Tcl, shell, Cadence, Mentor, Synopsys
3mo
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Emulation Verification Engineer
Cupertino or Sunnyvale or United States
OnsiteFull Time
10+ YOEBS with 10+ years in design verification; experience with SystemVerilog/UVM, emulation platforms, and verification environments.
Palladium, Veloce, Zebu, FPGA, Xilinx, Altera, Verilog, SystemVerilog, UVM, DPI, C/C++, Perl, Python, TCL
4d
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Design Verification Manager
Sunnyvale, California, United States
$174k-$353k/yr OnsiteFull Time
10+ YOE5+ Mgmt10+ years pre-silicon ASIC/SoC verification experience, 5+ years engineering management, expert SystemVerilog and UVM, formal verification, emulation platforms, SoC verification strategy and leadership.
SystemVerilog, Universal Verification Methodology (UVM), Palladium, Zebu, Veloce, Artificial Intelligence, Machine Learning, PCIe, CXL, HBM3, NVLink
1mo
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Design Verification Engineer
Lakeway or Austin
OnsiteFull Time
7+ YOEBSc/MSc in engineering or CS, 7+ years verification experience, expert SystemVerilog/UVM development, protocol verification (AXI, DDRx, PCIe, USBx), verification planning, and ability to travel; eligible to work in the US.
SystemVerilog, UVM, Specman/e, C, C++, Python, Perl
2d
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Principal Verification Engineer I
Westminster, Colorado, United States
$160k-$190k/yr OnsiteFull Time
9+ YOEBS in CS/EE/CE (MS preferred), 9+ years verification and automation experience, expert in FPGA/digital verification techniques and CI infrastructure.
VHDL, Verilog, SystemVerilog, C/C++, SystemC, UVM, UVMf, DPI-C, TLM, QEMU, VIP, MATLAB, Python, Linux, Xilinx, CI, HIL
1w
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Design Verification Engineer
Mountain View, California, United States
$120k-$475k/yr HybridFull Time
Concept-to-silicon verification experience with SystemVerilog, UVM, ABV, and scripting; production verification and silicon bring-up experience preferred.
SystemVerilog, Python, C/C++, Bluespec, UVM, assertion-based verification (ABV)
2mo
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Occupancy Verification Walker
Huntsville or United States
OnsiteContract
Independent contractor needed for residential occupancy verifications; must provide own vehicle and equipment; pass background check; self-managed schedule.
Mobile reporting apps, Smartphone, Printer, Internet connection
3mo
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Verification Pharmacist - FuzeRx
Sharonville, Ohio, United States
$61-$64/hr RemoteFull Time
Active pharmacist license; PharmD or BSPharm; experience in order verification and pharmacy workflows; proficiency with pharmacy systems; strong communication for hybrid work.
1mo
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ASIC Verification Engineer
Austin, Texas, United States
OnsiteFull Time
5+ YOE5+ years verification experience, 2+ full block/system verification cycles, deep VLSI verification knowledge, experience with SystemVerilog/UVM/eRM, familiarity with data-paths/protocols (Ethernet preferred), mentoring and cross-team collaboration.
SystemVerilog, UVM, eRM, RTL, Ethernet
2mo
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Staff Verification Engineer
Austin or Santa Clara
OnsiteFull Time
5+ YOE+5 years experience; BS/MS in CS/EE/CE; CPU verification; test plans and benches; IP verification; strong analytical skills.
SystemVerilog, C++, Python, Testbench
3d
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Staff Verification Engineer
Sunnyvale, California, United States
$179k-$219k/yr HybridFull Time
8+ YOE8+ years verification/software experience, strong Ruby/Python skills, deep Linux and networking knowledge, experience with ASIC drivers, mentorship and code-review experience.
Ruby, Python, C, Linux, Docker, Kubernetes, Viavi (Spirent TestCenter, Avalanche), Keysight (Ixia, Breaking Point), Wireshark, CI/CD
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