2mo
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Design Verification (DV) Engineer
Austin or Boulder or Chicago or London or New York City
$175k-$250k/yr OnsiteFull Time
2+ YOE2+ years RTL verification for FPGA/ASIC; SystemVerilog/UVM; Python; Linux; Verilator; Cocotb; C++ is a plus.
SystemVerilog, UVM, Python, Verilator, Cocotb, Linux, C++
2mo
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FPGA Engineer
Chicago, Illinois, United States
$175k-$225k/yr HybridFull Time
FPGA development experience (Verilog/VHDL), functional verification, static timing, PCIe; programming in C++/Python; strong problem-solving and collaboration.
Verilog, VHDL, PCIe, C++, Python, Synopsys, Riviera, ModelSim, QuestaSim
2w
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Systems Engineer (Oak Brook, IL, US)
Oak Brook, Illinois, United States
$108k-$144k/yr HybridFull Time
2+ YOEMaster's in relevant field plus 2 years engineering experience. Experience with system requirements, MATLAB/Simulink, CAN/CANFD/Canalyzer, system verification testing, vehicle-level electrical troubleshooting, and Jira.
MATLAB, Simulink, CAN, CANFD, Canalyzer, Jira, HIL
4w
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Product Development Engineer (Mechanical Design)
Schaumburg or Chicago
$85k-$140k/yr OnsiteFull Time
1+ YOEB.S. in Mechanical/Electrical engineering, 1+ years experience, SolidWorks and FEA (ANSYS) experience, GD&T and statistical methods, design for manufacturability, prototype verification, ability to travel up to 25%.
SolidWorks, ANSYS, FEA, Geometric Dimensioning and Tolerancing
1mo
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FPGA Engineer
Amsterdam or Chicago or London or New York City or Singapore
OnsiteFull Time
Professional FPGA/ASIC design and verification experience; SystemVerilog/Verilog/VHDL and C++; familiarity with EDA tools and scripting (TCL, Python, Bash); university degree in EE/CS/CE or related.
SystemVerilog, Verilog, VHDL, C++, TCL, Python, Bash, EDA
3w
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FPGA Engineer
Chicago, Illinois, United States
$120k-$170k/yr OnsiteFull Time
4+ YOE4+ years FPGA/ASIC experience, expert SystemVerilog and FPGA design, SoC and high-speed transceiver knowledge, simulation/verification skills, degree in EE/CE, strong analytical and collaboration skills.
SystemVerilog
2mo
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Senior FPGA Engineer
Chicago, Illinois, United States
$145k/yr OnsiteFull Time
10+ YOESenior FPGA/ASIC design with Verilog/SystemVerilog; RTL; timing; verification; Python/Bash; strong collaboration; BS in CS/EE; MS a plus.
Verilog, SystemVerilog, VHDL, Python, Bash, RTL
3w
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Hardware Engineer
Chicago, Illinois, United States
$200k-$225k/yr OnsiteFull Time
BS in EE/CE/CS or related, strong RTL design using SystemVerilog, C++ experience, verification and multi-clock-domain knowledge, Ethernet fundamentals, Python/Bash scripting, and strong debugging and collaboration skills.
SystemVerilog, C++, Python, Bash, FPGA, PMA (Physical Media Attachment), Ethernet, RTL
2mo
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FPGA Engineer (IL, Schaumburg)
Schaumburg, Illinois, United States
OnsiteFull Time
EndoSec: Security software and cryptographic hardware for government and defense.
Experience with RTL, C/C++, Python, VHDL/Verilog; hardware security; FPGA design and verification; system integration; cryptography concepts.
C/C++, Python, VHDL, Verilog, Tcl, Vivado, Questa, Quartus Prime, GHDL, Xilinx, Versal, Agilex, AXI, Avalon, cocotb, pyuvm