2,718 verification engineer jobs at 682 companies in United States
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Verification Engineer
San Jose, California, United States
OnsiteFull Time
3+ YOEBS/MS in ECE (or equivalent), 3+ years ASIC/SoC functional verification, strong UVM/SystemVerilog skills, testbench development, scripting in Python/Perl/TCL, and familiarity with regression/CI and hardware-assisted verification.
UVM, SystemVerilog, Python, Perl, TCL, Verilog-AMS, Palladium, Veloce, HAPS, Protium, UPF, UCIe, PCIe, CXL, Ethernet, UALink, VIP
3w
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Verification Engineer/Lead
North America or San Francisco or Austin or Boston
HybridFull Time
Experience owning block or subsystem verification in SoCs, driving verification for complex processors or high-performance ASICs, and performing performance verification; chip, chiplet, network, and multi-die verification preferred.
1w
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Principal Verification Engineer
Mountain View or Redmond or Hillsboro or Austin or Raleigh
$143k-$275k/yr HybridFull Time
3+ YOERequires a degree in electrical engineering, computer engineering, computer science, or related field and 3–8+ years of technical engineering experience depending on degree; verification, UVM, RTL, simulation, scripting, and security screening required.
Universal Verification Methodology (UVM), C, Zsh, Bash, Python, Perl, Verilog, Microsoft Azure, AXI, AMBA
1mo
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Verification Engineer
San Jose or Fort Collins
$122k-$195k/yr OnsiteFull Time
8+ YOEBachelor's in EE/EC or CS, 8+ years verification experience, SystemVerilog/UVM/OVM, Python/C/C++, strong debugging and communication skills.
System Verilog, UVM, OVM, Python, C, C++, ChatGPT, Gemini, Cursor
2mo
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Staff Verification Engineer
Pittsburgh, Pennsylvania, United States
$120k-$200k/yr OnsiteFull Time
5+ YOE5+ years ASIC/SoC verification experience, Bachelor’s or Master’s in electrical/computer engineering, expertise in SystemVerilog/UVM, constrained-random and assertion verification, scripting in Python/Perl/Tcl/shell, Cadence/Mentor/Synopsys tool experience, protocol knowledge (Ethernet, PCIe, CXL, AMBA).
SystemVerilog, UVM, Python, Perl, Tcl, shell, Cadence, Mentor, Synopsys
2w
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Design Verification Engineer
Santa Clara or Folsom or Austin
$166k-$250k/yr HybridFull Time
6+ YOEExperienced verification engineer with SystemVerilog, UVM, C/C++, Python or Perl, DDR memory verification, formal verification, and cross-functional hardware, firmware, and software collaboration experience.
SystemVerilog, UVM, C, C++, Python, Perl, DDR5, LPDDR5, LPDDR6, DFI, DIMMs, RTL, BIOS, GLS, NLP, XPROP, VIPs, BFMs
2w
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Senior Verification Engineer
Santa Clara, California, United States
$168k-$311k/yr HybridFull Time
10+ YOEBS/MS in engineering or computer science, 10+ years of relevant experience, and expertise in UVM, SystemVerilog, Verilog, Python, C/C++, verification methodologies, EDA tools, and display protocols.
UVM, SystemVerilog, Verilog, Python, C/C++, VCS, Verdi/Debussy, GDB
2w
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Sr Design Verification Engineer, HBM Verification Architecture
Richardson, Texas, United States
OnsiteFull Time
4+ YOEBachelor's degree in electrical or computer engineering, 4+ years of verification engineering experience, digital, analog, or mixed-signal verification, and 2+ years in custom or RTL verification flows.
Verilog, FastSpice, Generative AI, AI
2mo
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Design Verification Engineer
Lakeway or Austin
OnsiteFull Time
7+ YOEBSc/MSc in engineering or CS, 7+ years verification experience, expert SystemVerilog/UVM development, protocol verification (AXI, DDRx, PCIe, USBx), verification planning, and ability to travel; eligible to work in the US.
SystemVerilog, UVM, Specman/e, C, C++, Python, Perl
1mo
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Senior Verification Engineer
Wilmington, Massachusetts, United States
$110k-$152k/yr OnsiteFull Time
4+ YOE4+ years verification experience with SystemVerilog/UVM, RTL simulation and debug, scripting (Python/Perl/Tcl), SoC/processor verification, and strong analytical/debugging skills.
SystemVerilog, UVM, VCS, Xcelium, Simvision, Verdi, Questa, Python, Perl, Tcl, Linux, ARM Cortex-M, RISC-V, APB, AHB, AXI, QSPI, UART, DMA
6d
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Senior Principal Verification Engineer
Chandler, Arizona, United States
OnsiteFull Time
15+ YOEMS or PhD in electrical/computer engineering, 15+ years mixed-signal or analog verification experience, semiconductor verification expertise, leadership experience, and proficiency with RTL, behavioral, and gate-level simulation.
Real Number Model (RNM), AMS (Analog Mixed Signal), Gate-Level Simulation (GLS), RTL, Spectre, Xcelium, Verilog, SystemVerilog, SPICE, UVM
5d
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CPU Verification Engineer
Austin or Santa Clara
OnsiteFull Time
Requires a BS in electrical or computer engineering or equivalent experience; expertise in CPU verification, C/C++/assembly, Verilog, SystemVerilog, UVM, coverage, assertions, and verification flows.
C, C++, UVM, SystemVerilog, Verilog, Verilog simulator
2w
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AMS Verification Engineer
Richardson, Texas, United States
HybridFull Time
5+ YOEBachelor’s or Master’s in Electrical Engineering or related field; 5+ years in AMS verification, mixed-signal simulation, or IC development; Cadence tools and verification-flow experience; ITAR work eligibility.
Cadence, Python, Perl, Tcl, SKILL
5d
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Design Verification Engineer
Dallas, Texas, United States
OnsiteFull Time
1+ YOEBachelor's degree in electrical engineering or related field and 1+ year of AMS design verification experience. Preferred: SystemVerilog, UVM, RTL simulation, verification methodologies, and Python, Tcl, or Perl scripting.
SystemVerilog, UVM, Cadence Xcelium, Python, Tcl, Perl
2w
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Sr Design Verification Engineer, HBM Verification Architecture
Richardson, Texas, United States
OnsiteFull Time
4+ YOEBachelor's degree in electrical or computer engineering, 4+ years of verification experience, 3+ years in digital, analog, or mixed-signal verification, and 2+ years in custom or RTL verification flows.
Verilog, FastSpice, RTL2GDS, GenAI
5d
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Design Verification Engineer
Rancho Cordova, California, United States
$121k-$194k/yr HybridFull Time
3+ YOEMaster's degree with 3+ years or bachelor's degree with 5+ years in engineering or computer science; pre-silicon memory verification, UVM, SVA, formal verification, mixed-signal simulation, and scripting experience required.
UVM, SystemVerilog Assertions (SVA), Python, Perl, AI-assisted workflows
1mo
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Design Verification Engineer
Mountain View, California, United States
$120k-$475k/yr HybridFull Time
Concept-to-silicon verification experience; SystemVerilog, Python, C/C++, Bluespec; UVM and assertion-based verification; formal/simulated verification; portable test creation and silicon debug experience.
SystemVerilog, Python, C/C++, Bluespec, UVM, assertion-based verification (ABV)
1w
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Verification Engineer (CONTRACT)
Santa Clara, California, United States
$60k-$149k/yr OnsiteContract
5+ YOERequires 5–8 years of experience, strong SystemVerilog and UVM knowledge, debugging skills, protocol understanding, and experience developing verification environments, tests, coverage, and regressions.
SystemVerilog, UVM, VLSI, HVL
5d
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Senior Verification Engineer
Austin, Texas, United States
OnsiteFull Time
5+ YOEBSEE with 5+ years, MSEE with 3+ years, or PhD with 1+ years in semiconductor experience; expertise in Verilog/SystemVerilog, UVM/OVM, formal verification, Python, Perl, and UNIX/Linux.
Verilog, SystemVerilog, VHDL, OVM, UVM, Python, Perl, UNIX/Linux, DDR, PCIe, AMBA, CHI, ACE, AXI, SVA, AI, LLM
6d
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Technical Staff Engineer - Verification
Chandler or San Jose or San Jose or Roseville or Austin
$91k-$232k/yr OnsiteFull Time
12+ YOEBS or MS in electrical/electronic engineering and 12+ years verifying complex SoC designs. Requires SystemVerilog, UVM, formal verification, methodology development, automation, scripting, and SoC architecture expertise.
SystemVerilog, UVM, Python, TCL/TK, C, C++, Siemens, Cadence, Synopsys, Git, Perforce, svn, ARM, RISC-V, PCIe, DDR4, DDR5, LPDDR4X, MIPI DSI, MIPI CSI, Ethernet MAC, USB, FPGA, SoC, RTL, GDS
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