2mo
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ASIC Verification Engineer
Santa Clara, California, United States
$116k-$190k/yr HybridFull Time
2+ YOEBS or MS in EE/CS/CE; 2+ years verification; strong verification methodology experience; C++ and/or SystemVerilog; UVM; tools: VCS, Debussy, GDB; strong communication.
C++, SystemVerilog, VCS, Debussy, GDB, UVM, verification methodologies
1w
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Verification Engineer
San Jose or San Diego or Austin or Longmont
$124k-$213k/yr HybridFull Time
Experience in IP/ASIC/FPGA verification using UVM, Verilog/SystemVerilog, scripting (Python/Perl), and developing test plans and regression suites; bachelor’s or master’s in computer or electrical engineering.
UVM, Verilog, System Verilog, Python, Perl, PCIe, CXL, NVMe, Ethernet, HLS
2mo
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Verification Engineer
San Jose or Fort Collins
$120k-$192k/yr OnsiteFull Time
8+ YOEBS in Electrical/Electronic Eng or CS; 8+ years ASIC/RTL verification; SystemVerilog/UVM/OVM; Python/C++; block- and system-level verification; strong debugging and collaboration.
SystemVerilog, UVM, OVM, Python, C/C++, RTL
1w
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Verification Engineer
San Jose, California, United States
OnsiteFull Time
3+ YOEBS/MS in ECE (or equivalent), 3+ years ASIC/SoC functional verification, strong UVM/SystemVerilog skills, testbench development, scripting in Python/Perl/TCL, and familiarity with regression/CI and hardware-assisted verification.
UVM, SystemVerilog, Python, Perl, TCL, Verilog-AMS, Palladium, Veloce, HAPS, Protium, UPF, UCIe, PCIe, CXL, Ethernet, UALink, VIP
2w
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Staff Verification Engineer
Pittsburgh, Pennsylvania, United States
$120k-$200k/yr OnsiteFull Time
5+ YOE5+ years ASIC/SoC verification experience, Bachelor’s or Master’s in electrical/computer engineering, expertise in SystemVerilog/UVM, constrained-random and assertion verification, scripting in Python/Perl/Tcl/shell, Cadence/Mentor/Synopsys tool experience, protocol knowledge (Ethernet, PCIe, CXL, AMBA).
SystemVerilog, UVM, Python, Perl, Tcl, shell, Cadence, Mentor, Synopsys
2mo
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Test Verification Engineer
Boulder, Colorado, United States
$80k-$90k/yr OnsiteFull Time
3+ YOE3+ years in product test/verification; bachelor’s in Electrical/Mechanical/Quality Engineering or related; strong lab skills; automation/scripting experience; familiarity with AC up to 600 VAC.
Python, LabVIEW
1mo
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Design Verification Engineer
Lakeway or Austin
OnsiteFull Time
7+ YOEBSc/MSc in engineering or CS, 7+ years verification experience, expert SystemVerilog/UVM development, protocol verification (AXI, DDRx, PCIe, USBx), verification planning, and ability to travel; eligible to work in the US.
SystemVerilog, UVM, Specman/e, C, C++, Python, Perl
1mo
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Sr Principal Verification Engineer
Austin, Texas, United States
$171k-$296k/yr OnsiteFull Time
15+ YOEDesign verification of CPU cores; 15+ years exp; Bachelor's in Electronics/Electrical/Computer Engineering; SystemVerilog/UVM, scripting (Python/Perl/Shell); CPU/SoC verification experience.
SystemVerilog, UVM, Python, Perl, Shell, C, Assembly
2mo
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Principal Verification Engineer
Austin or Santa Clara
OnsiteFull Time
12+ YOE+12 years of experience; BS or MS in Computer Science, Electrical Engineering, or related field; experience with microarchitecture, CPU design, verification flow; strong analytical and troubleshooting skills; ability to collaborate across teams.
2mo
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ASIC verification engineer
Roseville, California, United States
$120k-$243k/yr OnsiteFull Time
6+ YOEBachelor's or Master's in Electrical/Computer Engineering; 6-10 years VLSI design/verification; Verilog/SystemVerilog/UVM; scripting (Python/Perl/TCL); C/C++; EDA/verification tools.
Verilog, SystemVerilog, UVM, Specman, Python, Perl, TCL, C, C++, EDA tools
3mo
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Formal Verification Engineer
Austin or Beaverton or Cupertino
OnsiteFull Time
0+ YOEBachelor's degree in electrical or computer engineering with 0 years of experience; strong Verification knowledge preferred.
2mo
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Design Verification Engineer (Data Fabric Verification Engineer)
Austin, Texas, United States
$45k-$121k/yr OnsiteFull Time
3+ YOE3-5 years VLSI/HVL verification experience; strong SystemVerilog and UVM skills; scripting with Perl, Ruby, or Make; familiarity with RTL, formal verification, and tools such as VCS, Cadence, and Mentor Graphics; bachelor's or master's in computer/electrical engineering preferred.
SystemVerilog, UVM, Perl, Ruby, Make, VCS, Cadence, Mentor Graphics
3w
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Verification Engineer Senior
Austin, Texas, United States
$191k-$269k/yr HybridFull Time
6+ YOEBachelor's in EE/CE/CS + 8+ yrs or Master's + 6+ yrs in ASIC/FPGA verification; SystemVerilog/UVM, OOP, coverage-driven verification, constrained-random testing, protocol experience (AXI, CHI, UART, SPI, I2C/I3C), strong debug skills.
SystemVerilog, UVM, Synopsys VCS, Cadence Xcelium
2mo
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ASIC verification engineer
Roseville, California, United States
$120k-$243k/yr OnsiteFull Time
6+ YOE Bachelor's or Master in Electrical or Computer Engineering; 6-10 years in VLSI design/verification; scripting and programming experience; strong VLSI knowledge.
Python, Perl, TCL, C, C++, Verilog, SystemVerilog, UVM, Specman
3mo
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Design Verification Engineer
Austin or Chandler or Greensboro
HybridFull Time
0+ YOEBachelor/Master/PhD in Electrical/Computer Engineering or related field; 2+ years with Bachelors; strong HDL/SystemVerilog/UVM; ASIC/silicon verification experience.
Verilog, VHDL, SystemVerilog, UVM
15h
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Senior Verification Engineer
Arlington, Virginia, United States
$146k-$234k/yr OnsiteFull Time
7+ YOEExtensive software/system verification experience, test planning and execution, automated test scripting, Agile experience, ability to obtain/maintain Secret clearance and upgrade to TS/SCI.
Linux, Postgres, MySQL, Selenium, Cypress, Jira, Jenkins, Gitlab, Ansible, Amazon Web Services (AWS), S3, Amazon RDS, Kubernetes, Docker
1d
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Design Verification Engineer
Mountain View, California, United States
$120k-$475k/yr HybridFull Time
Concept-to-silicon verification experience with SystemVerilog, UVM, ABV, and scripting; production verification and silicon bring-up experience preferred.
SystemVerilog, Python, C/C++, Bluespec, UVM, assertion-based verification (ABV)
1mo
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ASIC Verification Engineer
Austin, Texas, United States
OnsiteFull Time
5+ YOE5+ years verification experience, 2+ full block/system verification cycles, deep VLSI verification knowledge, experience with SystemVerilog/UVM/eRM, familiarity with data-paths/protocols (Ethernet preferred), mentoring and cross-team collaboration.
SystemVerilog, UVM, eRM, RTL, Ethernet
1mo
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Senior Verification Engineer
Austin, Texas, United States
OnsiteFull Time
5+ YOEBSEE+5yrs or MSEE+3yrs or PhD+1yr; expertise in Verilog/SystemVerilog, OVM/UVM, formal methods; knowledge of DDR, PCIe, AMBA; scripting in Python/Perl and UNIX/Linux; strong debugging and verification planning skills.
Verilog, SystemVerilog, VHDL, OVM/UVM, SystemVerilog assertions (SVA), DDR, PCIe, AMBA (CHI, ACE, AXI), AI/LLM, Python, Perl, UNIX/Linux
3mo
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GPU Verification Engineer
Westford, Massachusetts, United States
$136k-$265k/yr OnsiteFull Time
2+ YOEBachelor's degree (or equivalent) in EE/CE/CS, 2+–5+ years verification experience, proficiency in C/C++ and scripting (Perl/Python/shell), strong debugging and architecture/memory-model knowledge, VCS/emulation/FPGA exposure.
C, C++, Perl, Python, Shell, VCS, emulation, FPGA
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