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VLSI Design Engineer
Austin, Texas, United States
OnsiteFull Time
5+ YOE5+ years ASIC/VLSI digital design experience; strong Verilog/SystemVerilog; familiarity with simulation and verification methodologies, synthesis/timing analysis, and protocol implementation; BS/MS in EE/CE.
Verilog, SystemVerilog, Python, Perl, TCL, EDA tools, SDC, CDC, Linting, Formal Verification
1mo
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Microprocessor VLSI Physical Design Engineer
Fort Collins, Colorado, United States
HybridFull Time, Full Time
8+ YOEVLSI physical design engineer with strong analytic skills; experience in high-speed design and mentoring.
Verilog, Perl, C, Tcl
2w
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Senior Digital VLSI Design Engineer
Fort Collins or San Jose
$122k-$195k/yr OnsiteFull Time
8+ YOE8+ years VLSI experience with synthesis, DFT, CDC/RDC sign-off for high-speed IPs; BSEE required; EM/validation tool experience and mentoring skills.
SpyGlass CDC/RDC, Spyglass Lint, JasperGold, Meridian
1w
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VLSI LEAD L1
Santa Clara, California, United States
$60k-$149k/yr OnsiteFull Time
5+ YOELead VLSI development and board design; define architecture, layout and verification; 5+ years VLSI experience; team leadership and customer-facing support; familiarity with verification standards.
UVM
2mo
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VLSI Design Engineer for Server / Data Center Products
San Diego or Santa Clara or Austin
$140k-$210k/yr OnsiteFull Time
4+ YOEASIC/FPGA/RTL design experience for server/data center IPs, expertise in arithmetic/ML IPs, design for speed and power, scripting/tools for automation, and 3–5+ years ASIC design experience depending on degree.
1mo
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Senior Technologist Datapath Design Engineer and Circuit Design Engineer, VLSI Design Engineering
Milpitas, California, United States
$194k-$322k/yr OnsiteFull Time
15+ YOEMaster's in Electrical Engineering (or equivalent) with 15+ years experience; transistor/gate-level datapath and page-buffer design; RTL/Verilog, synthesis, static timing, silicon debugging, and high-speed I/O knowledge.
Verilog
2mo
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Senior Software R&D Engineer, VLSI Physical Design
Austin, Texas, United States
$168k-$311k/yr HybridFull Time
6+ YOEBS/MS/PhD in EE or CS (or equivalent), 6+ years VLSI algorithms development in C++, strong VLSI timing optimization knowledge, familiarity with ICC2/Innovus/PrimeTime/Tempus/StarRC and Perl/Tcl/Python, strong communication skills.
C++, C++14, ICC2, Innovus, PrimeTime, Tempus, StarRC, Perl, Tcl, Python, GNNs, reinforcement learning
2d
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Senior VLSI Library Methodology Engineer
Santa Clara, California, United States
$136k-$265k/yr OnsiteFull Time
4+ YOEM.S. (or equivalent) and 4+ years in library methodology, physical design, CAD or VLSI automation; strong software skills (Python/C++/Perl); experience with EDA tools and building scalable automation and validation systems.
Python, C++, Perl, Innovus, Fusion Compiler, Crosscheck, Virtuoso
2mo
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FPGA / VLSI Engineer
Saratoga, California, United States
$120k-$220k/yr OnsiteFull Time
Design and verify RTL/FPGA, perform FPGA prototyping, and system integration for ASIC/SoC platforms; strong SystemVerilog/Verilog; experience with UVM; VHDL is a plus.
SystemVerilog, Verilog, UVM, VHDL, FPGA, SoC
2mo
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Principal Engineer, ASIC/VLSI Synthesis and Design
San Diego, California, United States
$160k-$237k/yr OnsiteFull Time
5+ YOE10-15 years in ASIC implementation and synthesis; strong RTL-to-GDSII flow; experience with UPF, ECOs, STA; 5-10 years on advanced nodes; scripting.
Fusion Compiler, Conformal ECO, Conformal Low Power, UPF, Scripting (Tcl, Python)
1mo
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Group Technical Architect - AMS Mask Design (125832)
United States
OnsiteFull Time
Expertise in analog/mixed-signal VLSI design, EDA tools (Cadence, Synopsys), simulation and verification (DC/AC/transient/noise/stability), scripting (SKILL/Python/Perl) and end-to-end silicon validation.
Cadence Virtuoso, Cadence Spectre, Synopsys HSPICE, Synopsys PrimeSim, SKILL, Python, Perl
2mo
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CPU Memory Design Engineer
Austin, Texas, United States
$164k-$269k/yr HybridFull Time
6+ YOEBachelor's +6+ yrs or Master's +5+ yrs or PhD +2+ yrs; CMOS design; VLSI; memory design; power/performance/area trade-offs.
CMOS, VLSI, EDA tools, signal integrity
1w
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Wireless Design Verification Engineer
San Francisco, California, United States
OnsiteFull Time
Join a wireless system-on-chip team to drive energy-efficient silicon design, verification, emulation, and cross-discipline integration across RF/Analog, Systems/PHY/MAC, VLSI/RTL, and FW/SW domains.
VLSI, RTL, Emulation
3mo
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Principal Network Simulation Engineer - VLSI
Texas or Minnesota or California or Wisconsin
$174k-$353k/yr RemoteFull Time
10+ YOEBachelor’s/Master’s/PhD in Electrical or Computer Engineering; 10+ years of experience; proficient in C++ and Python; strong knowledge of network architecture and system-level design.
C++, Python
3mo
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Principal Network Simulation Engineer - VLSI
United States
$174k-$353k/yr RemoteFull Time
10+ YOEDevelop simulation models for NICs and switches; design and implement simulation motifs; create tools for performance analysis; evaluate architectures; collaborate with cross-functional teams.
C++, Python
3mo
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Digital Design Engineer
Austin or Greensboro or Chandler
HybridFull Time
2+ YOEDegree in Electrical or Computer Engineering; 2+ years digital IC design; Verilog RTL; digital design flow; state machines; CMOS VLSI knowledge; strong problem solving.
Verilog, UVM, MATLAB, Simulink
2w
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Staff Design Engineer, DRAM
Boise, Idaho, United States
OnsiteFull Time
5+ YOEBachelor's in EE/CE,5+ years CMOS/VLSI mixed-signal design experience including schematic, layout, simulation, power distribution, parasitic modeling, and tape-out flows.
Copilot, Claude
3mo
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ASIC design/verification engineer
Durham, North Carolina, United States
$135k-$311k/yr HybridFull Time
6+ YOEBachelor’s or Master’s degree in Electrical or Computer Engineering; 6-10 years in VLSI design/verification; strong HDL/EDA skills.
Hardware description language, Electronic design automation, FPGA tools, Programming and scripting
4w
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Physical Design Intern
San Jose, California, United States
$35-$45/hr OnsiteInternship
Currently pursuing a BS/MS in EE/CE or related field; foundational VLSI and ASIC physical design knowledge; scripting experience (Python, Perl, TCL); familiarity with ASIC flow and strong analytical/problem-solving skills.
Python, Perl, TCL, Synopsys ICC2, Cadence Innovus, PrimeTime, Tempus, LEF/DEF, UPF/CPF, GPT, Copilot
3mo
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Physical Design Engineer
Santa Clara, California, United States
OnsiteFull Time
4+ YOEBS/MS in EE/CS; 3-5 years experience; VLSI design/layout/timing; EDA tools Cadence/Synopsys; scripting; Verilog/VHDL; strong communication; CADENCE Innovus/Genus/Conformal and Synopsys Primetime/StarRC helpful.
Cadence Innovus, Quantus, Tempus, Synopsys Fusion Compiler, ICC2, StarRC, Primetime, Mentor Calibre, Genus, Conformal
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