80 vlsi engineer jobs at 18 companies in San Jose, CA
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VLSI LEAD L1
Santa Clara, California, United States
$60k-$149k/yr OnsiteFull Time
5+ YOELead VLSI development and board design; define architecture, layout and verification; 5+ years VLSI experience; team leadership and customer-facing support; familiarity with verification standards.
UVM
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Senior Digital VLSI Design Engineer
Fort Collins or San Jose
$122k-$195k/yr OnsiteFull Time
8+ YOE8+ years VLSI experience with synthesis, DFT, CDC/RDC sign-off for high-speed IPs; BSEE required; EM/validation tool experience and mentoring skills.
SpyGlass CDC/RDC, Spyglass Lint, JasperGold, Meridian
3mo
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FPGA / VLSI Engineer
Saratoga, California, United States
$120k-$220k/yr OnsiteFull Time
Design and verify RTL/FPGA, perform FPGA prototyping, and system integration for ASIC/SoC platforms; strong SystemVerilog/Verilog; experience with UVM; VHDL is a plus.
SystemVerilog, Verilog, UVM, VHDL, FPGA, SoC
3w
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Senior VLSI Library Methodology Engineer
Santa Clara, California, United States
$136k-$265k/yr OnsiteFull Time
4+ YOEM.S. (or equivalent) and 4+ years in library methodology, physical design, CAD or VLSI automation; strong software skills (Python/C++/Perl); experience with EDA tools and building scalable automation and validation systems.
Python, C++, Perl, Innovus, Fusion Compiler, Crosscheck, Virtuoso
3w
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Senior VLSI Library Methodology Engineer
Santa Clara, California, United States
$136k-$265k/yr OnsiteFull Time
4+ YOEM.S. or equivalent experience; 4+ years in library methodology, physical design, CAD, or VLSI automation; strong software skills in Python, C++, or Perl; hands-on EDA tool experience; experience building scalable automation and validation systems.
Python, C++, Perl, Innovus, Fusion Compiler, Crosscheck, Virtuoso
3mo
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VLSI Design Engineer for Server / Data Center Products
San Diego or Santa Clara or Austin
$140k-$210k/yr OnsiteFull Time
4+ YOEASIC/FPGA/RTL design experience for server/data center IPs, expertise in arithmetic/ML IPs, design for speed and power, scripting/tools for automation, and 3–5+ years ASIC design experience depending on degree.
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Senior Technologist Datapath Design Engineer and Circuit Design Engineer, VLSI Design Engineering
Milpitas, California, United States
$194k-$322k/yr OnsiteFull Time
15+ YOEMaster's in Electrical Engineering (or equivalent) with 15+ years experience; transistor/gate-level datapath and page-buffer design; RTL/Verilog, synthesis, static timing, silicon debugging, and high-speed I/O knowledge.
Verilog
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Wireless Design Verification Engineer
San Francisco, California, United States
OnsiteFull Time
Join a wireless system-on-chip team to drive energy-efficient silicon design, verification, emulation, and cross-discipline integration across RF/Analog, Systems/PHY/MAC, VLSI/RTL, and FW/SW domains.
VLSI, RTL, Emulation
3mo
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Product Test Development Engineer
San Jose, California, United States
$169k-$241k/yr HybridFull Time
9+ YOEBachelor’s or higher in Electrical/Computer Engineering; 9+ years in SOC/VLSI bring-up, characterization, and product engineering; strong Advantest 93000 tester experience.
Advantest 93000 tester, JMP
2d
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Sr. Silicon Design Engineer
Santa Clara, California, United States
$124k-$213k/yr OnsiteFull Time
1+ YOEMaster's degree in electronic, computer, or electrical engineering; 1 year of design engineering experience; VLSI, RTL, ASIC, Verilog, Python or Perl, EDA/CAD, and Unix/Linux experience.
Verilog, System Verilog, VHDL, Python, Perl, EDA, CAD, Unix, Linux
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Engineer II - Product
San Jose, California, United States
$70k-$143k/yr OnsiteFull Time
2.5+ YOEB.S. in Electrical Engineering, 2.5+ years semiconductor experience, strong digital/VLSI knowledge, Verilog/VHDL and EDA tool experience, failure analysis and yield analysis skills, lab test/debug experience.
Verilog, VHDL, Synopsis, Cadence Vrituoso
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Digital Design Engineer
San Jose, California, United States
$166k-$229k/yr OnsiteFull Time
Master's degree in electrical, electronics, or computer engineering required. Requires C/C++ or Python, Verilog, VLSI design, signal processing, digital and analog IC design, design automation, and computer architecture knowledge.
C, C++, Python, Verilog
2mo
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Senior Circuit Design Engineer - AI & HPC (7708) (San Jose, CA, US)
San Jose, California, United States
$120k-$165k/yr HybridFull Time
3+ YOEMaster’s with 3+ years or Ph.D. in VLSI design or related field; strong VLSI, digital IC, Verilog, DFT; SPICE simulations; collaborative; good communication.
Verilog, SPICE, EDA tools, Python, Perl, TCL
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Lead Engineer
Santa Clara, California, United States
$130k-$140k/yr OnsiteFull Time
8+ YOE8+ years physical design experience, expertise in Synopsys Fusion Compiler, low-power UPF methodologies, PPA optimization, strong Tcl/Python/Shell scripting, B.Tech/M.Tech in ECE/EE/VLSI, excellent communication and leadership.
Synopsys Fusion Compiler, Tcl, Python, Shell, PT, ICV, UPF
2mo
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Principal Product Engineer
San Jose, California, United States
$137k-$254k/yr OnsiteFull Time
2+ YOEExperience with digital implementation, logic synthesis, and timing closure; MS in EE/ECE with VLSI focus and 2+ years preferred; experience with Genus/Innovus, Perl, Tcl, shell scripting, Verilog/System Verilog; strong analysis and customer support skills.
Genus Synthesis Solution (Genus), Innovus, Perl, Tcl, shell scripting, Verilog, System Verilog
1w
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Advanced Physical Design and Verification Engineer (7036)
San Jose or California
$86k-$134k/yr HybridFull Time
Master’s degree in Electrical Engineering or Computer Science; knowledge of VLSI and physical design; research or internship experience; EDA tools; Python, Perl, or TCL programming; regular customer-site work.
Python, Perl, TCL, EDA, DRC, LVS, ERC, ANTENNA, EMIR, Netlist-GDS, P&R
2mo
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Senior Staff Test Engineer
San Jose, California, United States
$160k-$220k/yr OnsiteFull Time
10+ YOEBachelor's in EE or CS required (Master's preferred), 10+ years experience in semiconductor test/ATE, knowledge of semiconductor manufacturing, RF/analog, DFT, VLSI ATE, CAD/Allegro, and strong interpersonal skills.
Advantest 93K, Automatic Test Equipment (ATE), CAD, Allegro, PILOT
2w
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Analog Circuit Design Engineer
Santa Clara or Folsom
$122k-$232k/yr HybridFull Time
2+ YOEDegree in EE/CE with 2–3+ years VLSI analog design experience, familiarity with Synopsys and Cadence, small-signal analysis, high-speed IO and power delivery concepts, Matlab and scripting, and strong collaboration and documentation skills.
Synopsys, Cadence, Matlab, VS Code, Python, GitHub Copilot, oscilloscopes, signal generators
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ASIC Design Engineer (Video Silicon IP) - Multimedia Lab
San Jose, California, United States
OnsiteFull Time
2+ YOEM.S./Ph.D. in EE/CE, 2+ years ASIC front-end RTL ownership, proficiency in SystemVerilog/Verilog or HLS, familiarity with UVM/DPI/C++, Python scripting, and VLSI design concepts.
SystemVerilog, Verilog, High level Synthesis (HLS), UVM, DPI, C++, Python, AXI, APB, EDA, GitHub Copilot, Claude, ChatGPT, FPGA
2mo
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Principal Engineer – Multi-Physics Sign-off (Timing, PDN & Thermal)
San Jose or Austin or San Diego
$263k-$355k/yr HybridFull Time
5+ YOEVLSI knowledge with 5+ years system-level experience; hands-on 3DIC/2.5D design and signoff; strong scripting, flow ownership, and cross-team collaboration; familiarity with EDA tool qualification and multiphysics/thermal analysis.
Cadence Integrity 3D-IC, Synopsys 3DIC Compiler, Cadence Celsius Thermal Solver, Ansys Icepak, Ansys RHSC-ET
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