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VLSI Design Engineer
Austin, Texas, United States
OnsiteFull Time
5+ YOE5+ years ASIC/VLSI digital design experience; strong Verilog/SystemVerilog; familiarity with simulation and verification methodologies, synthesis/timing analysis, and protocol implementation; BS/MS in EE/CE.
Verilog, SystemVerilog, Python, Perl, TCL, EDA tools, SDC, CDC, Linting, Formal Verification
1w
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VLSI LEAD L1
Santa Clara, California, United States
$60k-$149k/yr OnsiteFull Time
5+ YOELead VLSI development and board design; define architecture, layout and verification; 5+ years VLSI experience; team leadership and customer-facing support; familiarity with verification standards.
UVM
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Microprocessor VLSI Physical Design Engineer
Fort Collins, Colorado, United States
HybridFull Time, Full Time
8+ YOEVLSI physical design engineer with strong analytic skills; experience in high-speed design and mentoring.
Verilog, Perl, C, Tcl
1w
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Senior Digital VLSI Design Engineer
Fort Collins or San Jose
$122k-$195k/yr OnsiteFull Time
8+ YOE8+ years VLSI experience with synthesis, DFT, CDC/RDC sign-off for high-speed IPs; BSEE required; EM/validation tool experience and mentoring skills.
SpyGlass CDC/RDC, Spyglass Lint, JasperGold, Meridian
2mo
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FPGA / VLSI Engineer
Saratoga, California, United States
$120k-$220k/yr OnsiteFull Time
Design and verify RTL/FPGA, perform FPGA prototyping, and system integration for ASIC/SoC platforms; strong SystemVerilog/Verilog; experience with UVM; VHDL is a plus.
SystemVerilog, Verilog, UVM, VHDL, FPGA, SoC
1mo
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Senior VLSI Methodology Engineer
Santa Clara, California, United States
$136k-$265k/yr OnsiteFull Time
4+ YOEM.S. in EE (or equivalent), 4+ years library/physical design/CAD methodology experience, hands-on with Innovus, Fusion Compiler, Crosscheck, Virtuoso, advanced Python/C++/Perl, and experience building automation and data pipelines.
Innovus, Fusion Compiler, Crosscheck, Virtuoso, Python, C++, Perl
3mo
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Principal Network Simulation Engineer - VLSI
Texas or Minnesota or California or Wisconsin
$174k-$353k/yr RemoteFull Time
10+ YOEBachelor’s/Master’s/PhD in Electrical or Computer Engineering; 10+ years of experience; proficient in C++ and Python; strong knowledge of network architecture and system-level design.
C++, Python
3mo
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Principal Network Simulation Engineer - VLSI
United States
$174k-$353k/yr RemoteFull Time
10+ YOEDevelop simulation models for NICs and switches; design and implement simulation motifs; create tools for performance analysis; evaluate architectures; collaborate with cross-functional teams.
C++, Python
1w
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VLSI Design Engineer for Server / Data Center Products
San Diego, California, United States
$140k-$210k/yr OnsiteFull Time
ASIC/FPGA design experience for server/data-center IPs, experience with arithmetic/machine-learning IPs, scripting for automation, and strong analytical and communication skills.
4w
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Senior Technologist Datapath Design Engineer and Circuit Design Engineer, VLSI Design Engineering
Milpitas, California, United States
$194k-$322k/yr OnsiteFull Time
15+ YOEMaster's in Electrical Engineering (or equivalent) with 15+ years experience; transistor/gate-level datapath and page-buffer design; RTL/Verilog, synthesis, static timing, silicon debugging, and high-speed I/O knowledge.
Verilog
1mo
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Principal Engineer, ASIC/VLSI Synthesis and Design
San Diego, California, United States
$160k-$237k/yr OnsiteFull Time
5+ YOE10-15 years in ASIC implementation and synthesis; strong RTL-to-GDSII flow; experience with UPF, ECOs, STA; 5-10 years on advanced nodes; scripting.
Fusion Compiler, Conformal ECO, Conformal Low Power, UPF, Scripting (Tcl, Python)
3mo
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Principal Network Simulation Engineer - VLSI
Texas or Minnesota or California or Wisconsin
$174k-$353k/yr RemoteFull Time
10+ YOE10+ years experience in electrical/computer engineering; expert in network simulation; proficient in C++ and Python; strong design and analysis of architectures.
C++, Python, Network simulation
3mo
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Formal Verification Engineer
Austin or Beaverton or Cupertino
OnsiteFull Time
10+ YOEBS degree and 10+ years in silicon validation software engineering; experience with formal methods; VLSI/digital logic; SoC design knowledge.
VLSI, Formal verification, SVA, PSL, EDA tools, Scripting languages
1mo
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Senior Full-Stack Software Engineer - VLSI Tools
Santa Clara or Westford or Austin or Durham
$152k-$288k/yr HybridFull Time
5+ YOE5+ years experience; BS/MS in Computer Science or related (or equivalent experience); knowledge of VLSI design; JavaScript, Node.js, modern frontend frameworks; distributed microservices, databases, algorithms; strong communication.
JavaScript, Node.js, Vue.js, React.js, Svelte, Ember.js, Cursor, Claude Code, Co-pilot, SQL, MongoDB, Python, Golang
1mo
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Staff Engineer (DTPG DOS STRAT Alignment)
Boise, Idaho, United States
HybridFull Time
2+ YOEMaster's in EE/Product/Computer Engineering + 2 years experience OR equivalent; proficiency in Python, Linux/Unix, VLSI design & EDA tools, data analysis, and Design for Test (DFT); drive cross-DRAM alignment and BKM propagation.
Python, Linux, Unix, VLSI Design, EDA Tools, Design for Test (DFT)
1mo
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CPU Memory Design Engineer
Austin, Texas, United States
$164k-$269k/yr HybridFull Time
6+ YOEBachelor's +6+ yrs or Master's +5+ yrs or PhD +2+ yrs; CMOS design; VLSI; memory design; power/performance/area trade-offs.
CMOS, VLSI, EDA tools, signal integrity
3w
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New College Grad - Product Yield Enhancement Engineer, HBM
Boise, Idaho, United States
OnsiteFull Time
0+ YOEBachelor's or Master's in engineering/physical science, 0-2 years semiconductor experience, CAD familiarity, UNIX/Linux scripting (Tcl, Bash, Shell), strong device physics and VLSI knowledge, failure analysis experience preferred.
CAD, UNIX, Linux, Tcl, Bash, Shell, emission microscopy, laser-based methods, EOTPR, VLSI
3w
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Group Technical Architect - AMS Mask Design (125832)
United States
OnsiteFull Time
Expertise in analog/mixed-signal VLSI design, EDA tools (Cadence, Synopsys), simulation and verification (DC/AC/transient/noise/stability), scripting (SKILL/Python/Perl) and end-to-end silicon validation.
Cadence Virtuoso, Cadence Spectre, Synopsys HSPICE, Synopsys PrimeSim, SKILL, Python, Perl
2w
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Engineer II - Design
Hauppauge, New York, United States
$70k-$143k/yr OnsiteFull Time
MS in Electrical or Computer Engineering required; coursework in analog/digital integrated circuits, VLSI, Verilog/System Verilog, VHDL; programming in C, Python, Perl, TCL; strong communication and teamwork; legal right to work in the US.
Verilog/System Verilog, VHDL, C, Python, Perl, TCL
2mo
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Product Test Development Engineer
San Jose, California, United States
$169k-$241k/yr HybridFull Time
9+ YOEBachelor’s or higher in Electrical/Computer Engineering; 9+ years in SOC/VLSI bring-up, characterization, and product engineering; strong Advantest 93000 tester experience.
Advantest 93000 tester, JMP
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