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Sr Staff Analog Engineer
San Jose, California, United States
$185k-$235k/yr HybridFull Time
10+ YOEMSEE +10 years experience in analog/mixed-signal design; strong analog design competence (motor drivers, power management, high-voltage/BCD), Cadence/EDA tool proficiency, AMS/ADC/DAC experience a plus, and strong communication skills.
Cadence, GreenPAK, EDA design tools
2mo
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Principal Analog Design Engineer
San Jose or United States
$175k-$350k/yr HybridFull Time
5+ YOE5+ years analog/mixed-signal IC design experience; strong analog fundamentals; proficiency with Spectre, HSPICE, ADE; post-layout closure and debug skills; cross-functional communication.
Spectre, HSPICE, ADE, waveform/debug tooling
1mo
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Staff Engineer, Analog design
San Jose, California, United States
$109k-$155k/yr OnsiteFull Time
5+ YOEMaster's (8+ yrs) or Ph.D. (5+ yrs) in EE, proven analog/mixed-signal IC tape-out experience, expertise in high-speed analog blocks, EDA tool proficiency, silicon characterization and lab validation experience.
SPICE, Spectre, Cadence Virtuoso, Mentor Graphics Calibre, Synopsys Custom Compiler, oscilloscopes, spectrum analyzers, network analyzers, parameter analyzers
1mo
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Sr. Analog Design Engineer
San Jose, California, United States
$120k-$180k/yr OnsiteFull Time
5+ YOEM.S. or Ph.D. in Electrical Engineering, 5+ years IC development with advanced CMOS (FinFET) experience; strong analog/mixed-signal circuit knowledge; proficiency with Cadence Virtuoso, Synopsys Custom Compiler, MATLAB, and Verilog.
Cadence Virtuoso, Synopsys Custom Compiler, MATLAB, Verilog
1mo
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Principal Engineer-Analog Design
San Jose, California, United States
$73k-$163k/yr OnsiteFull Time
10+ YOEBS in electrical engineering; 10+ years analog design; 5+ years mixed-signal CMOS; Cadence tools; nano CMOS FinFET experience.
Cadence, Circuit simulators
1mo
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Staff Analog Layout Engineer
San Jose or Hsinchu
OnsiteFull Time
3+ YOESenior/Staff level IC layout engineer with 3-8+ years in deep-submicron analog/RF layouts; strong EDA/tool experience and EM/IR knowledge.
Cadence Virtuoso, Synopsys Custom Compiler, Mentor Calibre, Siemens ICV
1mo
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Analog Circuit Design Engineer
San Jose, California, United States
$149k-$216k/yr OnsiteFull Time
10+ YOEBSEE/MSEE/PhD in Electrical Engineering or equivalent with 10+ years analog/mixed-signal design experience; experience with amplifiers, ADCs, regulators, SerDes; proficiency with Virtuoso, Spice, StarRC, Totem; Verilog and UPF knowledge.
Virtuoso, Spice, StarRC, Totem, Verilog, UPF, ICCT, IBIS
4d
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Senior Engineer, Analog Design Engineering
San Jose, California, United States
$157k-$190k/yr HybridFull Time
2+ YOEMaster's in EE or related field, 2 years analog design experience, expertise with transistor-level design and Cadence tools, silicon evaluation and lab test equipment, and participation in product development.
Cadence, spectrum analyzer, oscilloscope, signal generator, CMOS, BCD
1mo
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Analog Test & Characterization Engineer
San Jose, California, United States
$139k-$259k/yr HybridFull Time
2+ YOEMS with 2-3 years of experience or fresh PhD in EE/Physics; strong lab skills, PCB/debugging, scripting in Perl/LabVIEW/Python/MATLAB, analog/mixed-signal design knowledge, good communication and teamwork, HTOL/ESD experience, travel as needed.
Oscilloscopes, Network Analyzers, Phase Noise Analyzers, Power Supplies, Multimeters, Logic Analyzers, Perl, LabVIEW, Python, MATLAB
1mo
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Principal Analog Application Engineer for Custom / Electromagnetic flows
San Jose, California, United States
$123k-$229k/yr OnsiteFull Time
5+ YOEBS in Electrical/Computer Engineering required; 5+ years working with Cadence custom schematic and layout tools; knowledge of electromagnetic solvers and analog simulation; CAD setup and parasitic extraction experience desirable; strong communication and presentation skills.
Cadence custom schematic and layout tools, Cadence tools, CAD, electromagnetic solvers, analog simulation
1mo
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Principal Analog Design Engineer (Richardson, TX, US, 75081)
Richardson or San Jose
$170k-$222k/yr HybridFull Time
12+ YOEBachelor's in electrical engineering; 12+ years in semiconductor engineering; 8+ years in analog/mixed-signal IC design; strong communication; experience with EDA tools and PMIC design.
Cadence Virtuoso, Simplis, ADS, EMIR tools, parasitic extraction tools, capacitive coupling tools
2mo
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Principal Analog Design Engineer — Mixed-Signal PHY (Clocking / High-Speed I/O)
Boise or Folsom or Richardson or San Jose
$159k-$347k/yr OnsiteFull Time
10+ YOE10+ years analog/mixed-signal IC design; PLL/DLL/clocking; transistor-level simulations; analog-digital interfaces; lab data correlation
HSpice
2mo
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SMTS Analog Design Engineer, Mixed-Signal PHY (Clocking & High-Speed I/O)
Boise or Folsom or Richardson or San Jose
$159k-$347k/yr OnsiteFull Time
10+ YOEBS/MS/PhD in EE; 10+ years analog/mixed-signal IC design with tape-out; deep clocking (PLL/DLL/CDR) expertise; transistor-level simulation with HSpice; strong jitter analysis and analog-digital interface experience.
HSpice, Verilog-AMS, Real-number modeling (RNM)
1mo
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Principal Engineer, Analog/Mixed-Signal Design
San Jose, California, United States
$200k-$260k/yr OnsiteFull Time
12+ YOE12+ years in analog/mixed-signal design; MS/PhD in EE; production tapeouts in FinFET CMOS; Cadence experience; 50Gb/s or higher and RF 25GHz+ experience.
Cadence, ADE, Spectre
4w
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Principal/Senior High-Speed Analog Layout Engineer
Irvine or San Jose or Ottawa
OnsiteFull Time
10+ YOE10+ years analog/mixed-signal layout experience in advanced CMOS/FinFET (TSMC preferred), expertise with Cadence Virtuoso, Calibre, Pegasus, LVS/DRC/PERC/ERC flows, and leadership/mentoring experience; scripting with SKILL/TCL/Python a plus.
Cadence Virtuoso, Calibre, Pegasus, SKILL, TCL, Python
2mo
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Lead Principal Engineer Analog Mixed-Signal Design
San Jose or El Segundo or California
$190k-$262k/yr HybridFull Time
15+ YOEAdvanced degree (MSEE/PhD), 15+ years analog mixed-signal IC design experience (data converters), team management, ADC architecture and development, AMS IP for production, MATLAB/Simulink and hardware description language experience, strong communication skills.
MATLAB, Simulink, C, System Verilog, Verilog, VHDL
1mo
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Lead MTS Analog Engineering
San Jose, California, United States
$133k-$246k/yr HybridFull Time
Lead role for analog/mixed-signal design; strong experience with ESD/LU/EOS, ERC/DRC/LVS, and DDR products; capable of cross-functional collaboration across geographies.
fast simulator, CustomSim, XPS, AMS
2w
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Analog/mixed-signal IC Design Engineer - Acacia (Hybrid)
San Jose, California, United States
$169k-$241k/yr HybridFull Time
3+ YOEDegree (Bachelors+8 yrs, Masters+6 yrs, or PhD+3 yrs) in a relevant field; experience designing, simulating, and measuring high-speed analog/mixed-signal ICs; expertise in high-speed serial links, PLLs, output drivers, opamps, equalization, clocking; experience with Cadence, Spectre/APS/SpectreX, Calibre, EMX, AMS, and Matlab.
Cadence (Virtuoso), Virtuoso, Specture, APS, SpectreX, Calibre, EMX, AMS, Matlab
2mo
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Senior Director Analog IC Design
San Jose, California, United States
$224k-$280k/yr OnsiteFull Time
17+ YOE4+ MgmtBS/MS/PhD in Electrical Engineering; 17+ yrs analog/mixed-signal design; 4+ yrs leadership; SerDes, PLLs, ADC/DAC; FinFET; Cadence tools; strong leadership.
Cadence, Virtuoso, Spectre, Layout, Analog Modeling
2mo
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Applications Engineer
San Jose, California, United States
$120k-$140k/yr OnsiteFull Time
BS/B.E. in Electrical Engineering; hands-on analog power management; PCB design; good communication and teamwork.
PCB design tools, Laboratory equipment
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