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Sr. Engineer, ASIC Design
San Jose, California, United States
$160k-$192k/yr OnsiteFull Time
1+ YOEBS or MS in Electrical/Computer Engineering; 1+ years ASIC design; Verilog; ASIC verification tools; scripting; ability to work independently.
Verilog, Xcelium, VCS, Questa, Python, C, C++
2d
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ASIC Implementation Engineer STA
San Jose, California, United States
$144k-$230k/yr OnsiteFull Time
12+ YOEBachelor's in EE or Computer Engineering, 12+ years ASIC STA experience, proficiency with Cadence or Synopsys sign-off flows, SDC/constraint development, and scripting in Tcl, Python, or Perl.
Tcl, Python, Perl, Shell, Cadence, Synopsys
2w
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Staff Engineer - ASIC Verification
San Jose, California, United States
$139k-$259k/yr HybridFull Time
8+ YOEBachelor's in CS/EE required (Master's desired), 8+ years ASIC verification experience, fluent in System Verilog, UVM, Python/Perl, knowledge of assertions, functional/code coverage and formal verification tools, strong communication.
System Verilog, UVM, Python, Perl
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Senior ASIC Physical Design Engineer
San Jose or Austin or Research Triangle Park
$165k-$241k/yr OnsiteFull Time
1+ YOEDegree in Electrical or Computer Engineering with relevant ASIC experience (varies by degree), experience with EDA tools (Innovus, Tempus, PrimeTime, Redhawk, Voltus, Calibre, Pegasus), STA experience, and Python scripting.
Innovus, Tempus, PrimeTime, Redhawk, Voltus, Calibre, Pegasus, Tweaker, Static Timing Analysis (STA), Python, AI tools
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Sr. Staff ASIC Verification Engineer
Sunnyvale or San Jose or Munich
OnsiteFull Time
15+ YOE15+ years ASIC verification experience; expert in SystemVerilog and UVM; experience with SoC/subsystem verification, ARM/RISC-V, high-speed interfaces, C/C++/SystemC; scripting with Python/Perl/Tcl/Shell; BS required, MS preferred.
SystemVerilog, UVM, C, C++, SystemC, Python, Perl, Tcl, Shell
2mo
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Staff Engineer, ASIC Design Verification
San Jose, California, United States
$163k-$253k/yr OnsiteFull Time
10+ YOEBE/MS in Computer/Electrical Engineering or Computer Science; 10+ years in ASIC verification; strong UVM, C++ and SystemVerilog skills; SoC verification experience; memory/AI accelerator knowledge.
UVM, C++, SystemVerilog, SoC verification, Memory controller, DDR, HBM
2mo
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ASIC Verification Engineer
San Jose, California, United States
OnsiteFull Time
8+ YOE8+ years in UVM verification; RTL/gate-level verification; test plan and testbench development in C/Assembly/SystemVerilog; AMBA AXI/AHB/APB; PCIe/USB/Ethernet; scripting; repository and bug-tracking tools.
UVM, SystemVerilog, C, Assembly, Python, Shell, Perl, AMBA AXI, AHB, APB, PCIe, USB, Ethernet, DDR3/4, LPDDR, I2C/I3C, SPI, SD/SDIO/eMMC, UART, Git, JIRA, Bitbucket, Jenkins
1mo
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Sr. ASIC Design Engineer
San Jose, California, United States
$168k-$336k/yr OnsiteFull Time
5+ YOE5+ years experience; BS in Electrical Engineering or Computer Science; hands-on GenAI and agentic tool experience; proficient with EDA flows, SystemVerilog, simulation, synthesis, static timing analysis and top-level integration; AI/LLMs and interface protocol knowledge desirable.
GenAI, MCP, EDA, SystemVerilog, LLMs, PCIe, NVMe, DRAM, NAND, AXI, APR, DFT, LEC, CDC, linting
1mo
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ASIC Digital Design, Sr Staff Engineer
Noida or Bangalore or San Jose
OnsiteFull Time
8+ YOEBSEE/MSEE with 8+ years ASIC digital design experience; expertise in UCIe/PCIe/DDR/CXL/USB, SystemVerilog/Verilog, synthesis, CDC, formal, STA, Fusion Compiler, Perforce, and scripting (Perl/Shell).
SystemVerilog, Verilog, Fusion Compiler, Perforce, Perl, Shell
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Staff Engineer - ASIC Verification
San Jose or Folsom
$145k-$286k/yr OnsiteFull Time
6+ YOEBS in electrical engineering or computer science; 6-8 years verification; RTL debugging, scoreboarding, and code coverage; test plans and coverage definitions.
SystemVerilog, UVM, C, DDR, PCIe/NVMe, NAND
1w
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ASIC Design Engineer (Video Silicon IP) - Multimedia Lab
San Jose, California, United States
OnsiteFull Time
2+ YOEM.S./Ph.D. in EE/CE, 2+ years ASIC front-end RTL ownership, proficiency in SystemVerilog/Verilog or HLS, familiarity with UVM/DPI/C++, Python scripting, and VLSI design concepts.
SystemVerilog, Verilog, High level Synthesis (HLS), UVM, DPI, C++, Python, AXI, APB, EDA, GitHub Copilot, Claude, ChatGPT, FPGA
1d
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Sr. / Staff ASIC Digital Design Engineer
San Jose, California, United States
OnsiteFull Time
6+ YOEExpertise in DFT, synthesis, power and timing analysis; tapeout experience; scripting (tcl/perl/python/shell); UPF and STA; Bachelors+8 years or Masters+6 years in engineering.
Synopsys, Siemens Tessent, PT, DC, VCLP, Formality, LEC, PrimeClosure, PrimePower, VCS, VC-spyglass-dft, Tetramax, Tessent, UPF, UNIX, Linux, tcl, perl, python, shell
1mo
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Principal Engineer - Digital ASIC Design
San Jose, California, United States
$70k-$163k/yr OnsiteFull Time
10+ YOE10+ years ASIC/FPGA digital design; SystemVerilog; Cadence/Synopsys front-end; PHY/Serdes knowledge; post-silicon validation; travel up to 25%.
System Verilog, Cadence Tools, Synopsys Tools, VCS, SpyGlass, Design Compiler, PrimeTime, Lab equipment
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Senior ASIC Verification Engineer
San Jose, California, United States
RemoteFull Time
8+ YOE8+ years in networking hardware verification; UVM/SystemVerilog; RTL debugging; complex SoCs; Git/SVN; BS in CE/CS/EE.
UVM, SystemVerilog, VCS, Verdi, Git, SVN, Python, TCL, Perl, Shell, TCP/IP, RDMA, RoCE, IPSec
2mo
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ASIC Technical Program Manager
San Jose, California, United States
OnsiteFull Time
5+ YOEAt least one full ASIC tape-out; RTL-to-GDSII know-how; 5+ years in technical/program management in semiconductor or hardware; external vendor interaction; strong communication; startup pace adaptability; Bachelor in Engineering/CS.
RTL, GDSII, DFT, EDA tools
3d
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Chief Engineering Lead - Sr Director ASIC Product Development
San Jose or Austin
OnsiteFull Time
15+ YOEBS/MS in Electrical Engineering or Computer Science, 15 years ASIC/SoC experience, proven program and people leadership, strong SoC/product development, analytical and communication skills.
1mo
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Senior Hardware Engineer (Teradyne, San Jose, CA) (San Jose, CA, US)
San Jose, California, United States
$111k-$178k/yr OnsiteFull Time
5+ YOEB.S. or M.S. in electrical engineering (or relevant field), 5+ years hardware/board design experience, high-speed digital/analog/power/FPGA/ASIC design, PCB and SI/PI experience, strong communication and mentorship skills.
DDR, PCIe, USB, SerDes, FPGA, ASIC, PCB, Signal integrity (SI), Power integrity (PI)
1mo
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Sr. Hardware Engineer, Networking Swtich (San Jose, California, United States)
San Jose, California, United States
$155k-$175k/yr OnsiteFull Time
8+ YOEBachelor's in EE or related, 8+ years hardware design for networking/server/HPC; PCB schematic/layout, SI/PI, thermal co-design, hardware bring-up, validation, ASIC/FPGA/CPLD experience, CPO/optics, Linux familiarity.
Oscilloscope, Logic Analyzer, Protocol Analyzer, Linux, Verilog, ASIC, FPGA, CPLD
1w
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Verification Engineer
San Jose, California, United States
OnsiteFull Time
3+ YOEBS/MS in ECE (or equivalent), 3+ years ASIC/SoC functional verification, strong UVM/SystemVerilog skills, testbench development, scripting in Python/Perl/TCL, and familiarity with regression/CI and hardware-assisted verification.
UVM, SystemVerilog, Python, Perl, TCL, Verilog-AMS, Palladium, Veloce, HAPS, Protium, UPF, UCIe, PCIe, CXL, Ethernet, UALink, VIP
1mo
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Senior Principal Design Engineer
Austin or San Jose
OnsiteFull Time
7+ YOEASIC design with Verilog; deep Cadence/Synopsys P&R knowledge; RTL-to-GDS flows; multi-volt and low power; 7+ years experience; BS degree.
Verilog, Cadence Encounter, Genus, Static Timing Analysis, Synthesis, Place and Route, CTS, DFT, Scan
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